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70V9369L6PFGI Datasheet(PDF) 7 Page - Integrated Device Technology |
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70V9369L6PFGI Datasheet(HTML) 7 Page - Integrated Device Technology |
7 / 17 page 6.42 IDT70V9369L High-Speed 3.3V 16K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges 7 AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing)(3) (VDD = 3.3V ± 0.3V) NOTES: 1. Transitionismeasured0mVfromLoworHigh-impedancevoltagewiththeOutputTestLoad(Figure2).Thisparameterisguaranteedbydevicecharacterization,butisnotproduction tested. 2. ThePipelinedoutputparameters(tCYC2,tCD2)applytoeitherorboththeLeftandRightportswhenFT/PIPE=VIH.Flow-throughparameters(tCYC1,tCD1)applywhenFT/PIPE=VILfor thatport. 3. AllinputsignalsaresynchronouswithrespecttotheclockexceptfortheasynchronousOutputEnable(OE),FT/PIPER,andFT/PIPEL. 70V9369L6 Com'l Only 70V9369L7 Com'l Only & Ind 70V9369L9 Com'l Only 70V9369L12 Com'l Only Symbol Parameter Min.Max.Min.Max.Min.Max.Min. Max. Unit tCYC1 Clock Cycle Time (Flow-Through)(2) 19 ____ 22 ____ 25 ____ 30 ____ ns tCYC2 Clock Cycle Time (Pipelined)(2) 10 ____ 12 ____ 15 ____ 20 ____ ns tCH1 Clock High Time (Flow-Through)(2) 6.5 ____ 7.5 ____ 12 ____ 12 ____ ns tCL1 Clock Low Time (Flow-Through)(2) 6.5 ____ 7.5 ____ 12 ____ 12 ____ ns tCH2 Clock High Time (Pipelined)(2) 4 ____ 5 ____ 6 ____ 8 ____ ns tCL2 Clock Low Time (Pipelined)(2) 4 ____ 5 ____ 6 ____ 8 ____ ns tR Clock Rise Time ____ 3 ____ 3 ____ 3 ____ 3ns tF Clock Fall Time ____ 3 ____ 3 ____ 3 ____ 3ns tSA Address Setup Time 3.5 ____ 4 ____ 4 ____ 4 ____ ns tHA Address Hold Time 0 ____ 0 ____ 1 ____ 1 ____ ns tSC Chip Enable Setup Time 3.5 ____ 4 ____ 4 ____ 4 ____ ns tHC Chip Enable Hold Time 0 ____ 0 ____ 1 ____ 1 ____ ns tSW R/W Setup Time 3.5 ____ 4 ____ 4 ____ 4 ____ ns tHW R/W Hold Time 0 ____ 0 ____ 1 ____ 1 ____ ns tSD Input Data Setup Time 3.5 ____ 4 ____ 4 ____ 4 ____ ns tHD Input Data Hold Time 0 ____ 0 ____ 1 ____ 1 ____ ns tSAD ADS Setup Time 3.5 ____ 4 ____ 4 ____ 4 ____ ns tHAD ADS Hold Time 0 ____ 0 ____ 1 ____ 1 ____ ns tSCN CNTEN Setup Time 3.5 ____ 4 ____ 4 ____ 4 ____ ns tHCN CNTEN Hold Time 0 ____ 0 ____ 1 ____ 1 ____ ns tSRST CNTRST Setup Time 3.5 ____ 4 ____ 4 ____ 4 ____ ns tHRST CNTRST Hold Time 0 ____ 0 ____ 1 ____ 1 ____ ns tOE Output Enable to Data Valid ____ 6.5 ____ 7.5 ____ 9 ____ 12 ns tOLZ Output Enable to Output Low-Z(1) 2 ____ 2 ____ 2 ____ 2 ____ ns tOHZ Output Enable to Output High-Z(1) 17 17 17 17 ns tCD1 Clock to Data Valid (Flow-Through)(2) ____ 15 ____ 18 ____ 20 ____ 25 ns tCD2 Clock to Data Valid (Pipelined)(2) ____ 6.5 ____ 7.5 ____ 9 ____ 12 ns tDC Data Output Hold After Clock High 2 ____ 2 ____ 2 ____ 2 ____ ns tCKHZ Clock High to Output High-Z(1) 29 29 292 9 ns tCKLZ Clock High to Output Low-Z(1) 2 ____ 2 ____ 2 ____ 2 ____ ns Port-to-Port Delay tCWDD Write Port Clock High to Read Data Delay ____ 24 ____ 28 ____ 35 ____ 40 ns tCCS Clock-to-Clock Setup Time ____ 9 ____ 10 ____ 15 ____ 15 ns 5648 tbl 11 |
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