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709169L9PFI Datasheet(PDF) 9 Page - Integrated Device Technology |
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709169L9PFI Datasheet(HTML) 9 Page - Integrated Device Technology |
9 / 16 page 6.42 IDT709169/59L High-Speed 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges 9 Timing Waveform of Read Cycle for Flow-Through Output (FT/PIPE"X" = VIL)(3,6) Timing Waveform of Read Cycle for Pipelined Operation (FT/PIPE"X" = VIH)(3,6) NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 3. ADS = VIL, CNTEN and CNTRST = VIH. 4. The output is disabled (High-Impedance state) by CE0 = VIH or CE1 = VIL following the next rising edge of the clock. Refer to Truth Table 1. 5. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 6. "X" here denotes Left or Right port. The diagram is with respect to that port. An An + 1 An + 2 An + 3 R/ W ADDRESS DATAOUT OE tCD1 tCKLZ Qn Qn + 1 Qn + 2 tOHZ tOLZ tOE tCKHZ 5653 drw 07 (1) (1) (1) (1) (2) tSW tHW tSA tHA tDC tDC (5) tCYC1 tCH1 tCL1 CE0 CLK tSC tHC CE1 tSC tHC An An + 1 An + 2 An + 3 R/ W ADDRESS DATAOUT OE tCD2 tCKLZ Qn Qn + 1 Qn + 2 tOHZ tOLZ tOE 5653 drw 08 (1) (1) (1) (2) tSW tHW tSA tHA tDC (5) (1 Latency) (6) tCYC2 tCH2 tCL2 CE0 CLK CE1 (4) tSC tHC tSC tHC |
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