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70V9389L7PRFG8 Datasheet(PDF) 1 Page - Integrated Device Technology |
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70V9389L7PRFG8 Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 19 page ©2014 Integrated Device Technology, Inc. MARCH 2014 DSC-4856/8 1 Functional Block Diagram Features: ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location ◆ High-speed clock to data access – Commercial: 7.5/9/12ns (max.) – Industrial: 9ns (max.) ◆ Low-power operation – IDT70V9389/289L Active: 500mW (typ.) Standby: 1.5mW (typ.) ◆ Flow-Through or Pipelined output mode on either port via the FT/PIPE pins ◆ Counter enable and reset features ◆ Dual chip enables allow for depth expansion without additional logic ◆ LVTTL- compatible, single 3.3V (±0.3V) power supply ◆ Full synchronous operation on both ports – 4ns setup to clock and 0ns hold on all control, data, and addressinputs – Data input, address, and control registers – Fast 7.5ns clock to data out in the Pipelined output mode – Self-timedwriteallowsfastcycletime – 12ns cycle time, 83MHz operation in Pipelined output mode ◆ Separate upper-byte and lower-byte controls for multiplexed bus and bus matching compatibility ◆ Industrial temperature range (–40°C to +85°C) is available for selected speeds ◆ Available in a 128-pin Thin Quad Flatpack (TQFP) and 100-pin Thin Quad Flatpack (TQFP) ◆ Green parts available, see ordering information IDT70V9389/289L 0a 1a 0b 1b 0/1 ab I/O Control 1 0/1 0 FT/PIPER R/WR UBR LBR CE0R OER CE1R MEMORY ARRAY Counter/ Address Reg. 4856 drw 01 A15R A0R CLKR ADSR CNTENR CNTRSTR I/O9L-I/O17L(2) I/O0L-I/O8L(1) I/O9R-I/O17R(1) I/O0R-I/O8R(1) A15L Counter/ Address Reg. R/WL UBL LBL CE0L OEL CE1L 1 0/1 0 1b 0b 1a 0a 0/1 ba I/O Control FT/PIPEL A0L CLKL ADSL CNTENL CNTRSTL HIGH-SPEED 3.3V 64K x18/x16 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM NOTES: 1. I/O0X - I/O7X for IDT70V9289. 2. I/O8X - I/O15X for IDT70V9289. |
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