70V3589S166DRG8 datasheet(5/23 Pages) IDT

Part #	70V3589S166DRG8

Description	HIGH-SPEED 3.3V 128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM

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Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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6.42

5

High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM

Industrial and Commercial Temperature Ranges

IDT70V3599/89S

Pin Names

Left Port

Right Port

Names

CE0L,

CE1L

CE0R,

CE1R

Chip Enables(5)

R/WL

R/WR

Read/Write Enable

OEL

OER

Output Enable

A0L - A16L(1)

A0R - A16R(1)

Address

I/O0L - I/O35L

I/O0R - I/O35R

Data Input/Output

CLKL

CLKR

Clock

PL/FTL

PL/FTR

Pipeline/Flow-Through

ADSL

ADSR

Address Strobe Enable

CNTENL

CNTENR

Counter Enable

REPEATL

REPEATR

Counter Repeat(4)

BE0L

- BE3L

BE0R

- BE3R

Byte Enables (9-bit bytes)(5)

VDDQL

VDDQR

Power (I/O Bus) (3.3V or 2.5V)(2)

OPTL

OPTR

Option for selecting VDDQX(2,3)

VDD

Power (3.3V)(2)

VSS

Ground (0V)

TDI

Test Data Input

TDO

Test Data Output

TCK

Test Logic Clock (10MHz)

TMS

Test Mode Select

TRST

Reset (Initialize TAP Controller)

5617 tbl 01

NOTES:

1. A16 is a NC for IDT70V3589.

2. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to

applying inputs on the I/Os and controls for that port.

3. OPTX selects the operating voltage levels for the I/Os and controls on that port.

If OPTX is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V

levels and VDDQX must be supplied at 3.3V. If OPTX is set to VIL (0V), then that

port's I/Os and address controls will operate at 2.5V levels and VDDQX must be

supplied at 2.5V. The OPT pins are independent of one another—both ports can

operate at 3.3V levels, both can operate at 2.5V levels, or either can operate

at 3.3V with the other at 2.5V.

4. When REPEATX is asserted, the counter will reset to the last valid address loaded

via ADSX.

5. Chip Enables and Byte Enables are double buffered when PL/FT = VIH, i.e., the

signals take two cycles to deselect.

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