70V9079L6PFGI datasheet(5/19 Pages) IDT

Part #	70V9079L6PFGI

Description	HIGH-SPEED 3.3V 64/32K x 8 SYNCHRONOUS DUAL-PORT STATIC RAM

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Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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5 / 19 page

6.42

IDT70V9089/79S/L

High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

5

NOTES:

1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input

levels of GND to 3V.

2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.

3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. ICC DC(f=0) = 90mA (Typ).

5. CEX = VIL means CE0X = VIL and CE1X = VIH

CEX

= VIH means CE0X = VIH or CE1X = VIL

CEX

< 0.2V means CE0X < 0.2V and CE1X > VDD - 0.2V

CEX

> VDD - 0.2V means CE0X > VDD - 0.2V or CE1X < 0.2V

"X" represents "L" for left port or "R" for right port.

6. 'X' in part number indicates power rating (S or L).

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range(6) (VDD = 3.3V ± 0.3V)

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (VDD = 3.3V ± 0.3V)

NOTE:

1. At VDD < 2.0V input leakages are undefined.

Symbol

Parameter

Test Conditions

70V9089/79S

70V9089/79L

Unit

Min.

Max.

Min.

Max.

|ILI|

Input Leakage Current(1)

VDD = 3.3V, VIN = 0V to VDD

___

10

___

5µA

|ILO|

Output Leakage Current

CE0

= VIH or CE1 = VIL, VOUT = 0V to VDD

___

10

___

5µA

VOL

Output Low Voltage

IOL = +4mA

___

0.4

___

0.4

V

VOH

Output High Voltage

IOH = -4mA

2.4

___

2.4

___

V

3750 tbl 08

70V9089/79X6

Com'l Only

70V9089/79X7

Com'l Only

70V9089/79X9

Com'l Only

Symbol

Parameter

Test Condition

Version

Typ.(4)

Max.

Typ.(4)

Max.

Typ.(4)

Max.

Unit

ICC

Dynamic Operating

Current

(Both Ports Active)

CEL

and CER = VIL

Outputs Disabled

f = fMAX(1)

COM'L

S

L

220

395

350

200

335

290

180

260

225

mA

IND

S

L

____

ISB1

Standby Current

(Both Ports - TTL

Level Inputs)

CEL

and CER = VIH

f = fMAX(1)

COM'L

S

L

70

145

130

60

115

100

50

75

65

mA

IND

S

L

____

ISB2

Standby Current

(One Port - TTL

Level Inputs)

CE"A"

= VIL and

CE"B"

= VIH(3)

Active Port Outputs Disabled,

f=fMAX(1)

COM'L

S

L

150

280

250

130

240

210

110

170

150

mA

IND

S

L

____

ISB3

Full Standby Current

(Both Ports -

CMOS Level Inputs)

Both Ports CER and

CEL

> VDD - 0.2V

VIN > VDD - 0.2V or

VIN < 0.2V, f = 0(2)

COM'L

S

L

1.0

0.4

5

3

1.0

0.4

5

3

1.0

0.4

5

3

mA

IND

S

L

____

ISB4

Full Standby Current

(One Port -

CMOS Level Inputs)

CE"A"

< 0.2V and

CE"B"

> VDD - 0.2V(5)

VIN > VDD - 0.2V or

VIN < 0.2V, Active Port

Outputs Disabled, f = fMAX(1)

COM'L

S

L

140

270

240

120

230

200

100

160

140

mA

IND

S

L

____

3750 tbl 09a

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