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PERICOMPI7C8150 Datasheet(PDF) 7 Page - Pericom Semiconductor Corporation |
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PERICOMPI7C8150 Datasheet(HTML) 7 Page - Pericom Semiconductor Corporation |
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7 / 106 page  PI7C8150 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION vii August 22, 2002 – Revision 1.02 14.1.43 RETRY COUNTER REGISTER – OFFSET 78h .......................................................... 78 14.1.44 PRIMARY MASTER TIMEOUT COUNTER – OFFSET 80h ..................................... 79 14.1.45 SECONDARY MASTER TIMEOUT COUNTER – OFFSET 80h ............................... 79 14.1.46 CAPABILITY ID REGISTER – OFFSET B0h ............................................................. 79 14.1.47 NEXT POINTER REGISTER – OFFSET B0h ............................................................. 79 14.1.48 SLOT NUMBER REGISTER – OFFSET B0h .............................................................. 79 14.1.49 CHASSIS NUMBER REGISTER – OFFSET B0h ....................................................... 80 14.1.50 CAPABILITY ID REGISTER – OFFSET DCh............................................................. 80 14.1.51 NEXT ITEM POINTER REGISTER – OFFSET DCh ................................................. 80 14.1.52 POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET DCh ................. 80 14.1.53 POWER MANAGEMENT DATA REGISTER – OFFSET E0h................................... 80 14.1.54 CAPABILITY ID REGISTER – OFFSET E4h ............................................................. 81 14.1.55 NEXT POINTER REGISTER – OFFSET E4h ............................................................. 81 15 BRIDGE BEHAVIOR.................................................................................................................... 81 15.1 BRIDGE ACTIONS FOR VARIOUS CYCLE TYPES .............................................................. 81 15.2 ABNORMAL TERMINATION (INITIATED BY BRIDGE MASTER).................................... 82 15.2.1 MASTER ABORT................................................................................................................ 82 15.2.2 PARITY AND ERROR REPORTING ................................................................................ 82 15.2.3 REPORTING PARITY ERRORS ....................................................................................... 82 15.2.4 SECONDARY IDSEL MAPPING ...................................................................................... 83 16 IEEE 1149.1 COMPATIBLE JTAG CONTROLLER................................................................ 83 16.1 BOUNDARY SCAN ARCHITECTURE..................................................................................... 83 16.1.1 TAP PINS............................................................................................................................. 84 16.1.2 INSTRUCTION REGISTER............................................................................................... 84 16.2 BOUNDARY SCAN INSTRUCTION SET ................................................................................ 85 16.3 TAP TEST DATA REGISTERS.................................................................................................. 85 16.4 BYPASS REGISTER ................................................................................................................... 86 16.5 BOUNDARY-SCAN REGISTER................................................................................................ 86 16.6 TAP CONTROLLER ................................................................................................................... 86 17 ELECTRICAL AND TIMING SPECIFICATIONS................................................................... 90 17.1 MAXIMUM RATINGS ............................................................................................................... 90 17.2 DC SPECIFICATIONS................................................................................................................ 90 17.3 AC SPECIFICATIONS................................................................................................................ 91 17.4 66MHZ TIMING.......................................................................................................................... 91 17.5 33MHZ TIMING.......................................................................................................................... 92 17.6 POWER CONSUMPTION .......................................................................................................... 92 18 PACKAGE INFORMATION........................................................................................................ 92 18.1 208-PIN FQFP PACKAGE DIAGRAM ...................................................................................... 92 18.2 256-BALL PBGA PACKAGE DIAGRAM ................................................................................. 93 18.3 PART NUMBER ORDERING INFORMATION........................................................................ 93 LIST OF TABLES Table 3-1. Pin list – 208-pin FQFP_______________________________________________________ 7 Table 3-2. Pin list – 208-pin FQFP_______________________________________________________ 9 Table 4-1. PCI Transactions ___________________________________________________________ 11 Table 4-2. Write Transaction Forwarding ________________________________________________ 12 Table 4-3. Write Transaction Disconnect Address Boundaries ________________________________ 15 Table 4-4. Read Prefetch Address Boundaries _____________________________________________ 16 |
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