H = HIGH Voltage Level

L = LOW Voltage Level

X = Don’t Care

Z = High Impedance (off)

Address inputs S0 and S1

are common to both sections.

4-121

FAST AND LS TTL DATA

MC54/74F253

9

7

1

6

2

10

14

11

LOGIC DIAGRAM

OEb

13b

12b

11b

10b

S0

S1

13a

12a

11a

10a

OEa

Za

Zb

VCC = PIN 16

GND = PIN 8

= PIN NUMBERS

3

4

5

12

13

15

FUNCTIONAL DESCRIPTION

The F253 contains two identical 4-input Multiplexers with

3-State Outputs. They select two bits from four sources se-

lected by common Select Inputs (S0, S1). The 4-input multi-

plexers have individual Output Enable (OEa, OEb) inputs

which, when HIGH, force the outputs to a high impedance

(high Z) state.

The F253 is the logic implementation of a 2-pole, 4-position

switch, where the position of the switch is determined by the

logic levels supplied to the two select inputs. The logic equa-

tions for the outputs are shown below:

Za = OEa • (I0a • S1 • S0 + I1a • S1 • S0 +

I2a • S1 • S0 + 13a • S1 • S0)

Zb = OEb • (I0b • S1 • S0 + I1b • S1 • S0 +

I2b • S1 • S0 + I3b • S1 • S0)

If the outputs of 3-state devices are tied together, all but one

device must be in the high impedance state to avoid high cur-

rents that would exceed the maximum ratings. Designers

should ensure that Output Enable signals to 3-state devices

whose outputs are tied together are designed so that there is

no overlap.

FUNCTION TABLE

Select

Inputs

Data Inputs

Output

Enable

Output

S0

S1

I0

I1

I2

I3

OE

Z

X

X

X

X

X

X

H

Z

L

L

L

X

X

X

L

L

L

L

H

X

X

X

L

H

H

L

X

L

X

X

L

L

H

L

X

H

X

X

L

H

L

H

X

X

L

X

L

L

L

H

X

X

H

X

L

H

H

H

X

X

X

L

L

L

H

H

X

X

X

H

L

H