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DLPR910YVA Datasheet(PDF) 3 Page - Texas Instruments |
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DLPR910YVA Datasheet(HTML) 3 Page - Texas Instruments |
3 / 17 page A B C D E F G H 1 2 3 4 5 6 3 DLPR910 www.ti.com DLPS065B – SEPTEMBER 2015 – REVISED NOVEMBER 2016 Product Folder Links: DLPR910 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated (1) P = Power G = Ground I = Input O = Output 5 Pin Configuration and Functions YVA Package 48-Pin DSBGA Top View Pin Functions PIN TYPE(1) DESCRIPTION NAME NO. GND A1 G Ground GND A2 G Ground OE/RESET A3 I/O Output Enable/RESET (Open-Drain I/O). When Low, this input holds the address counter reset and the DATA and CLKOUT outputs are placed in a high-impedance state. This is a bidirectional open-drain pin that is held Low while the PROM completes the internal power-on reset sequence. Polarity is not programmable. Pin must be pulled High using an external 4.7-kΩ pull-up to VCCO. DNC A4 — Do Not Connect. Leave unconnected. D6 A5 — Do Not Connect. Leave unconnected. D7 A6 — Do Not Connect. Leave unconnected. VCCINT B1 P Positive 1.8-V supply voltage for internal logic. VCCO B2 P Positive 3.3-V and 1.8-V supply voltage connected to the output voltage drivers and internal buffers. CLK B3 I Configuration clock input. Each rising edge on the CLK input increments the internal address counter. Pin must be pulled High and Low using an external 100-Ω pull-up to VCCO and an external 100-Ω pull-down to Ground. Place resistors close to pin. (CE) B4 I Chip Enable Input. When (CE ) is High, the device is put into low-power standby mode, the address counter is reset, and the DATA and CLKOUT outputs are placed in a high impedance state. D5 B5 — Do Not Connect. Leave unconnected. GND B6 G Ground |
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