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OPA316-Q1, OPA2316-Q1, OPA4316-Q1

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SBOS841A – NOVEMBER 2016 – REVISED JANUARY 2017

Product Folder Links: OPA316-Q1 OPA2316-Q1 OPA4316-Q1

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(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2)

The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3)

The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4)

The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5)

(6)

(7)

The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

6.4 Thermal Information: OPA316-Q1

OPA316-Q1

UNIT

DBV (SOT-23)

5 PINS

221.7

°C/W

144.7

°C/W

49.7

°C/W

26.1

°C/W

49

°C/W

N/A

°C/W