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X84256ZI Datasheet(PDF) 4 Page - Xicor Inc. |
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X84256ZI Datasheet(HTML) 4 Page - Xicor Inc. |
4 / 15 page X84256 Preliminary 4 The nonvolatile write cycle is initiated by issuing a special read/write “1”/read sequence. The first read cycle ends the page load, then the write “1” followed by a read starts the nonvolatile write cycle. The device recognizes 64- byte pages (e.g., beginning at addresses XXXXXXXXX 000000 for X84256). When sending data to the part, attempts to exceed the upper address of the page will result in the address counter “wrapping-around” to the first address on the page, where data loading can continue. For this reason, sending more than 512 consecutive data bits will result in overwriting previous data. A nonvolatile write cycle will not start if a partial or incom- plete write sequence is issued. The internal write enable latch is reset when the nonvolatile write cycle is com- pleted and after an invalid write to prevent inadvertent writes. Note that this sequence is fully static, with no spe- cial timing restrictions. The processor is free to perform other tasks on the bus whenever the chip enable pin (CE) is HIGH. Nonvolatile Write Status The status of a nonvolatile write cycle can be determined at any time by simply reading the state of the l/O pin on the device. This pin is read when OE and CE are LOW and WE is HIGH. During a nonvolatile write cycle the l/O pin is LOW. When the nonvolatile write cycle is complete, the l/O pin goes HIGH. A reset sequence can also be issued during a nonvolatile write cycle with the same result: I/O is LOW as long as a nonvolatile write cycle is in progress, and l/O is HIGH when the nonvolatile write cycle is done. Low Power Operation The device enters an idle state, which draws minimal current when: • an illegal sequence is entered. The following are the more common illegal sequences: —Read/Write/Write—any time —Read/Write ‘1’—When writing the address or writ- ing data. Figure 2. Write Sequence CE OE WE I/O (IN) "0" "0" "1" RESET LOAD ADDRESS LOAD DATA START NONVOLATILE WRITE A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 I/O (OUT) WHEN ACCESSING: X84256 ARRAY: A15=0 A15 A14 A13 A12 A11 A10 A9 SYMBOL TABLE WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance |
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