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UPSD3233B-24T6T Datasheet(PDF) 8 Page - STMicroelectronics |
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UPSD3233B-24T6T Datasheet(HTML) 8 Page - STMicroelectronics |
8 / 176 page µPSD323X 8/176 Product Term Allocator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... .... ... . . . . . . . . ... .. . . ... 125 CPLD Output Macrocell (Figure 61.) . . . . . . . . . . . . . . . . . . . . . . . . . .... .... .. . . . . . . . . .... 125 Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Input Macrocell (Figure 62.). . . . . . . . . . . . . . . . . . . . . . . . . .... .... ... . ... .. . . ... .. . .... 126 I/O PORTS (PSD MODULE) . . . . . . . .... . ... .. . . ... ... . ... .. . . ... .. . .... . ... .. .. ... ..127 General Port Architecture . . . . . . . . . . . . . . . . . . . . .... . . . ... . . . . . . . . . . . . . ... ... . . . ...127 General I/O Port Architecture (Figure 63.). . . . ... .. .... ... . . . . . . . . . . . . . . . . . . . . ... .. . . 127 Port Operating Modes . . . . . . . . . .... . ... .. . . . . .... .... .. . .... .. . . . . . . ... .. . .... . . 128 MCU I/O Mode. .... .. . . . . . . . . .... . ... .. . . . . .... .... .. . .... .. . . . . . . ... .. . . . . . ..128 PLD I/O Mode . .... .. . .... .. . .... . ... .. . . . . . ... . ... .. . . ... .. . .... . ... .. . . ... ..128 Address Out Mode. . . . . . . . . . . . .... . ... .. . . . . .... .... .. . . . . . . . . . . . . . ... .. . .... . . 128 Peripheral I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . .... . . . ... . . . . . . . . . . . . . ... ... . . . ...128 JTAG In-System Programming (ISP) . . . . . . . . . . . . .... ... . . . . . . . . . . . . . . . . . . . . ... .. . . 128 Peripheral I/O Mode (Figure 64.). .... . ... .. . . ... ... . ... .. .. ... .. . . ... . ... . . . . ... ..129 Port Operating Modes (Table 92.) . . . . . . . . . . . . . . .... .... .. . . . . . . . . . . . . . ... .. . .... . . 129 Port Operating Mode Settings (Table 93.). . . . . . . . .... .... .. . . . . . . . . . . . . . ... .. . .... . . 129 I/O Port Latched Address Output Assignments (Table 94.) . . . . . . . . . . . . . . . . . . . . . . . .... . . 129 Port Configuration Registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... . ... .. . . ... ..130 Port Configuration Registers (PCR) (Table 95.) . . . . . . . . . . . . . . . . . . . . . . . . . .... . . ... .. .. 130 Port Pin Direction Control, Output Enable P.T. Not Defined (Table 96.) . . . . . . . .... . . ... .. .. 130 Port Pin Direction Control, Output Enable P.T. Defined (Table 97.) . . . . . . . . . . . . . . . . . . . . . . . 130 Port Direction Assignment Example (Table 98.) . . . . . . . . . . . . . . . . . . . . . . . . . .... . . ... .. .. 130 Port Data Registers . . . .... ... . . . . . . . . ... .. . . ... . . . .... . . . .... .... .. . .... .. . .... 131 Drive Register Pin Assignment (Table 99.) . . . . . . . . .... ... . . . ... .. .. .. .. . . . . . . ... . ...131 Ports A and B – Functionality and Structure . . . . . . .... . . . ... . . . . . . . . . . . . . ... ... . . . ...132 Port A and Port B Structure (Figure 65.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...132 Port C – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... . ... .. .. ... ..133 Port C Structure (Figure 66.) . . . . . . . . . . . . . . . . . . . . . . . . .... .... ... . . . . . . . . ... .. . . ... 133 Port D – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... . ... .. .. ... ..134 Port D Structure (Figure 67.) . . . . . . . . . . . . . . . . . . . . . . . . .... .... ... . . . . . . . . ... .. . . ... 134 External Chip Select . . . . . . . . . . . . . . . . . . . . . . . . .... . . . ... . . . . . . . . . . . . . ... ... . . . ...135 Port D External Chip Select Signals (Figure 68.) . . . . ... . . . . . . . . . .... ... . . . . . . . . . . . . . . 135 POWER MANAGEMENT . . . . . . . . . .... . ... .. . . ... ... . ... .. . . ... .. . . ... . ... .. .. ... ..136 APD Unit (Figure 69.) . . . . . . . . . .... . ... .. . . ... ... . ... .. .. ... .. . . ... . ... .. .. ... ..136 Enable Power-down Flow Chart (Figure 70.) . . . . . . .... ... . . . . . . . . . . . . . . . . . . . . ... .. . . 137 Power-down Mode’s Effect on Ports (Table 101.) . . . . . . . . . . . . . . . . . . . . . . . . . . . .... . ... ..137 PLD Power Management . . . . . . . . . . . . . . . . . . . . . .... ... . . . . . . . . . . . . . . . . . . . . ... .. . . 138 PSD Chip Select Input (CSI, PD2) . . . .... . . ... .. ... .. .. . . . . . . . ... .. .. .... . . ... .. .. 138 Input Clock. . . . . . . . . . . . . . .... . . .. .. ... .. .. .. .. . . . . . . ... . . . . . . . . . ... .. .. ... .. .. 138 Input Control Signals . . . . . .... . . . . .. . . . . . . . . . . . . . ... ... . . . . . . . . . . . . ... .. . . . . . . . . 138 Power Management Mode Registers PMMR01 (Table 102.) . . . . .... .. . . . . . . ... .. . .... . . 138 Power Management Mode Registers PMMR21 (Table 103.) . . . . .... .. . . . . . . ... .. . .... . . 139 APD Counter Operation (Table 104.) . . . . . . . ... . . . . . . . . . ... .. .. ... .. . ... .. . . ... .. .. 139 |
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