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BQ3285LF Datasheet(PDF) 6 Page - Texas Instruments

Part # BQ3285LF
Description  Y2K-Enhanced Real-Time Clock (RTC)
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

BQ3285LF Datasheet(HTML) 6 Page - Texas Instruments

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On the next update cycle, the RTC updates all 10 bytes
in the selected format.
32kHz Output
The bq3285LF provides for a 32.768kHz output, and the
output is always active whenever VCC is valid (VPFD +
tCSR). The bq3285LF output is not affected by the bit
settings in Register A. Time-keeping aspects, however,
still require setting OS0-OS2.
Interrupts
The bq3285LF allows three individually selected inter-
rupt events to generate an interrupt request.
These
three interrupt events are:
n
The periodic interrupt, programmable to occur once
every 122
µs to 500ms.
n
The alarm interrupt, programmable to occur once per
second to once per day, is active in battery-backup
mode, providing a “wake-up” feature.
n
The update-ended interrupt, which occurs at the end
of each update cycle.
Each of the three interrupt events is enabled by an indi-
vidual interrupt-enable bit in register B. When an event
occurs, its event flag bit in register C is set. If the corre-
sponding event enable bit is also set, then an interrupt
request is generated.
The interrupt request flag bit
(INTF) of register C is set with every interrupt request.
Reading register C clears all flag bits, including INTF,
and makes INT high-impedance.
Two methods can be used to process bq3285LF interrupt
events:
n
Enable interrupt events and use the interrupt
request output to invoke an interrupt service routine.
n
Do not enable the interrupts and use a polling routine
to periodically check the status of the flag bits.
The individual interrupt sources are described in detail
in the following sections.
Periodic Interrupt
If the periodic interrupt event is enabled by writing a 1
to the periodic interrupt enable bit (PIE) in register C,
an interrupt request is generated once every 122
µsto
500ms. The period between interrupts is selected with
bits RS3-RS0 in register A (see Table 3).
6
Register A Bits
Periodic Interrupt
OSC2
OSC1
OSC0
RS3
RS2
RS1
RS0
Period
Units
0100
0
0
0
None
0100
0
0
1
3.90625
ms
0100
0
1
0
7.8125
ms
0100
0
1
1
122.070
µs
0100
1
0
0
244.141
µs
0100
1
0
1
488.281
µs
0100
1
1
0
976.5625
µs
0100
1
1
1
1.95315
ms
0101
0
0
0
3.90625
ms
0101
0
0
1
7.8125
ms
0101
0
1
0
15.625
ms
0101
0
1
1
31.25
ms
0101
1
0
0
62.5
ms
0101
1
0
1
125
ms
0101
1
1
0
250
ms
0101
1
1
1
500
ms
011
X
X
X
X
same as above defined
by RS3–RS0
Table 3. Periodic Interrupt Rate
bq3285LF


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