DS2165Q

2 of 17

OVERVIEW

The DS2165Q contains three major functional blocks: a high performance (10 MIPS) DSP engine, two

independent PCM interfaces (X and Y) that connect directly to serial time-division-multiplexed (TDM)

backplanes, and a serial port that can configure the device on-the-fly by an external controller. A 10MHz

master clock is required by the DSP engine. The DS2165Q can be configured to perform either two

expansions, two compressions, or one expansion and one compression. The PCM/ADPCM data interfaces

support data rates from 256kHz to 4.096MHz. Typically, the PCM data rates are 1.544MHz for

m-law and

2.048MHz for A-law. Each channel on the device samples the serial input PCM or ADPCM bit stream

during a user-programmed input time slot, processes the data and outputs the result during a user-

programmed output time slot.

Each PCM interface has a control register that specifies functional characteristics (compress, expand,

bypass, and idle), data format (

m-law or A-law), and algorithm reset control. With the SPS pin strapped

high, the software mode is enabled and the serial port can be used to configure the device. In this mode, a

novel addressing scheme allows multiple devices to share a common 3-wire control bus, simplifying

system-level interconnect.

With SPS low, the hardware mode is enabled. This mode disables the serial port and maps certain control

register bits to some of the address and serial port pins. Under the hardware mode, no external host

controller is required and all PCM/ADPCM input and output time slots default to time slot 0.

HARDWARE RESET

RST

allows the user to reset both channel algorithms and the contents of the internal registers. This pin

must be held low for at least 1ms on system power-up after the master clock is stable to ensure that the

both channels are set to 1.

SOFTWARE MODE

Connecting SPS high enables the software mode. In this mode, an external host controller writes

write to the DS2165Q is either a 2-byte write or a 4-byte write. A 2-byte write consists of the

address/command byte (ACB), followed by a byte to configure the control register (CR) for either the X

or Y channel. The 4-byte write consists of the ACB, followed by a byte to configure the CR, and then 1

byte to set the input time slot and another byte to set the output time slot.

ADDRESS/COMMAND BYTE

In the software mode, the address/command byte is the first byte written to the serial port; it identifies

which of the 64 possible ADPCM processors sharing the port wiring is to be updated. Address data must

match that at inputs A0 to A5. If no match occurs, the device ignores the following configuration data. If

an address match occurs, the next 3 bytes written are accepted as control, input and output time slot data.

Bit ACB.6 determines which side (X or Y) of the device is to be updated. The PCM and ADPCM outputs

are tri-stated during register updates.