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DS4000 Datasheet(PDF) 4 Page - Dallas Semiconductor |
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DS4000 Datasheet(HTML) 4 Page - Dallas Semiconductor |
4 / 16 page DS4000 Digitally Controlled TCXO 4 of 16 AC ELECTRICAL CHARACTERISTICS—2-WIRE SERIAL INTERFACE (VCC = 4.75 to 5.25V, TA = -40 °C to +85°C) PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS Fast mode 0 400 SCL Clock Frequency fSCL Standard mode 0 100 kHz Fast mode 1.3 Bus Free Time Between a STOP and START Condition tBUF Standard mode 4.7 ms Fast mode (Note 7) 0.6 Hold Time (Repeated) START Condition tHD:STA Standard mode (Note 7) 4.0 ms Fast mode 1.3 Low Period of SCL Clock tLOW Standard mode 4.7 ms Fast mode 0.6 High Period of SCL Clock tHIGH Standard mode 4.0 ms Fast mode 0.6 Setup Time for a Repeated START Condition tSU:STA Standard mode 4.7 ms Fast mode (Note 8) 0 0.9 Data Hold Time tHD:DAT Standard mode (Note 8) 0 0.9 ms Fast mode (Note 9) 100 Data Setup Time tSU:DAT Standard mode (Note 9) 250 ns Fast mode (Note 9) 20 + 0.1CB 300 Rise Time of Both SDA and SCL tR Standard mode (Note 9) 20 + 0.1CB 1000 ns Fast mode (Note 10) 20 + 0.1CB 300 Fall Time of Both SDA and SCL tF Standard mode (Note 10) 20 + 0.1CB 1000 ns Fast mode 0.6 Setup Time for STOP Condition tSU:STO Standard mode 4.0 ms Capacitive Load for Each Bus Line CB (Note 10) 400 pF Input Capacitance CI 5 pF Note 7: After this period, the first clock pulse is generated. Note 8: The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal. Note 9: A fast-mode device can be used in a standard mode system, but the requirement tSU:DAT >250ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tRMAX + tSU:DAT (1000 + 250 = 1250ns) before the SCL line is released. Note 10: CB: Total capacitance of one bus line in pF. |
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