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71T75602100BGI8 Datasheet(PDF) 1 Page - Integrated Device Technology |
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71T75602100BGI8 Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 23 page  APRIL 2012 DSC-5313/10 1 ©2012 Integrated Device Technology, Inc. A0-A19 Address Inputs Input Synchronous CE1 , CE2, CE2 Chip Enables Input Synchronous OE Output Enable Input Asynchronous R/W Read/Write Signal Input Synchronous CEN Clock Enable Input Synchronous BW1 , BW2, BW3, BW4 Individual Byte Write Selects Input Synchronous CLK Clock Input N/A ADV/LD Advance burst address / Load new address Input Synchronous LBO Linear / Interleaved Burst Order Input Static TMS Test Mode Select Input N/A TDI Test Data Input Input N/A TCK Test Clock Input N/A TDO Test Data Input Output N/A TRST JTAG Reset (Optional) Input Asynchronous ZZ Sleep Mode Input Synchronous I/O0-I/O31, I/OP1-I/OP4 Data Input / Output I/O Synchronous VDD, VDDQ Core Power, I/O Power Supply Static VSS Ground Supply Static 5313 tbl 01 Pin Description Summary Features • 512K x 36, 1M x 18 memory configurations • Supports high performance system speed - 200 MHz (3.2 ns Clock-to-Data Access) • ZBTTM Feature - No dead cycles between write and read cycles • Internally synchronized output buffer enable eliminates the need to control OE • Single R/W (READ/WRITE) control pin • Positive clock-edge triggered address, data, and control signal registers for fully pipelined applications • 4-word burst capability (interleaved or linear) • Individual byte write (BW1 - BW4) control (May tie active) • Three chip enables for simple depth expansion • 2.5V power supply (±5%) • 2.5V I/O Supply (VDDQ) • Power down controlled by ZZ input • Boundary Scan JTAG Interface (IEEE 1149.1 Compliant) • Packaged in a JEDEC standard 100-pin plastic thin quad flatpack (TQFP), 119 ball grid array (BGA) IDT71T75602 IDT71T75802 512K x 36, 1M x 18 2.5V Synchronous ZBT™ SRAMs 2.5V I/O, Burst Counter Pipelined Outputs Description The IDT71T75602/802 are 2.5V high-speed 18,874,368-bit (18 Megabit)synchronousSRAMs.Theyaredesignedtoeliminatedead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, they have been given the name ZBTTM, or Zero Bus Turnaround. Address and control signals are applied to the SRAM during one clock cycle, and two cycles later the associated data cycle occurs, be it read or write. The IDT71T75602/802 contain data I/O, address and control signal registers.Outputenableistheonlyasynchronoussignalandcanbeused todisabletheoutputsatanygiventime. A Clock Enable CEN pin allows operation of the IDT71T75602/802 tobesuspendedaslongasnecessary.Allsynchronousinputsareignored when(CEN)ishighandtheinternaldeviceregisterswillholdtheirprevious values. There are three chip enable pins (CE1, CE2, CE2) that allow the usertodeselectthedevicewhendesired.Ifanyoneofthesethreeisnot assertedwhenADV/LDislow,nonewmemoryoperationcanbeinitiated. However,anypendingdatatransfers(readsorwrites)willbecompleted. |
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