71V547S85PFG8 datasheet(11/20 Pages) IDT

Part #	71V547S85PFG8

Description	Synchronous SRAM

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Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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11 / 20 page

6.42

11

IDT71V547, 128K x 36, 3.3V Synchronous SRAM with

ZBT



 Feature, Burst Counter and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

NOTES:

1. H = High; L = Low; X = Don’t Care; ? = Don't Know; Z = High Impedance.

2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.

3. Device outputs are ensured to be in High-Z during device power-up.

Read Operation with Chip Enable Used(1)

NOTES:

1. H = High; L = Low; X = Don’t Care; ? = Don't Know; Z = High Impedance.

2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.

Write Operation with Chip Enable Used(1)

Cycle

Address

R/W

ADV/LD

CE(1)

CEN

BW

x

OE

I/O(3)

Comments

n

X

L

H

L

X

?

Deselected

n+1

X

L

H

L

X

Z

Deselected

n+2

A0

H

L

X

Z

Address A0 and Control meet setup

n+3

X

L

H

L

X

L

Q0

Address A0 read out. Deselected

n+4

A1

H

L

X

Z

Address A1 and Control meet setup

n+5

X

L

H

L

X

L

Q1

Address A1 Read out. Deselected

n+6

X

L

H

L

X

Z

Deselected

n+7

A2

H

L

X

Z

Address A2 and Control meet setup

n+8

X

L

H

L

X

L

Q2

Address A2 read out. Deselected

n+9

X

L

H

L

X

Z

Deselected

3822 tbl 18

Cycle

Address

R/W

ADV/LD

CE(1)

CEN

BW

x

OE

I/O

Comments

n

X

L

H

L

X

?

Deselected

n+1

X

L

H

L

X

Z

Deselected

n+2

A0

L

X

Z

Address A0 and Control meet setup

n+3

X

L

H

L

X

D0

Address D0 Write In. Deselected

n+4

A1

L

X

Z

Address A1 and Control meet setup

n+5

X

L

H

L

X

D1

Address D1 Write In. Deselected

n+6

X

L

H

L

X

Z

Deselected

n+7

A2

L

X

Z

Address A2 and Control meet setup

n+8

X

L

H

L

X

D2

Address D2 Write In. Deselected

n+9

X

L

H

L

X

Z

Deselected

3822 tbl 19

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