6.42

3

IDT71V547, 128K x 36, 3.3V Synchronous SRAM with

ZBT

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 Feature, Burst Counter and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

NOTE:

1. All synchronous inputs must meet specified setup and hold times with respect to CLK.

Symbol

Pin Function

I/O

Active

Description

Address Inputs

I

N/A

Synchronous Address inputs. The address register is triggered by a combination

of the rising edge of CLK, ADV/LD Low, CEN Low and true chip enables.

ADV/LD

Address/Load

I

N/A

ADV/LD is a synchronous input that is used to load the internal registers with new

address and control when it is sampled low at the rising edge of clock with the

chip selected. When ADV/LD is low with the chip deselected, any burst in

progress is terminated. When ADV/LD is sampled high then the internal burst

counter is advanced for any burst that was in progress. The external addresses

are ignored when ADV/LD is sampled high.

R/W

Read/Write

I

N/A

R/W signal is a synchronous input that identifies whether the current load cycle

initiated is a Read or Write access to the memory array. The data bus activity for

the current cycle takes place one clock cycle later.

CEN

Clock Enable

I

LOW

Synchronous Clock Enable Input. When CEN is sampled high, all other

synchronous inputs, including clock are ignored and outputs remain unchanged.

The effect of CEN sampled high on the device outputs is as if the low to high

clock transition did not occur. For normal operation, CEN must be sampled low at

rising edge of clock.

Individual Byte

Write Enables

I

LOW

Synchronous byte write enables. Enable 9-bit byte has its own active low byte

write enable. On load write cycles (When R/W and ADV/LD are sampled low) the

must also be valid on each cycle of a burst write. Byte Write signals are ignored

when R/W is sampled high. The appropriate byte(s) of data are written into the

entire 36-bit word.

Chip Enables

I

LOW

ADV/LD low at the rising edge of clock, initiates a deselect cycle. This device has

a one cycle deselect, i.e., the data bus will tri-state one clock cycle after deselect

is initiated.

CE2

Chip Enable

I

HIGH

CLK

Clock

I

N/A

This is the clock input to the IDT71V547. Except for OE, all timing references for

the device are made with respect to the rising edge of CLK.

Data Input/Output

I/O

N/A

Data input/output (I/O) pins. The data input path is registered, triggered by the

rising edge of CLK. The data output path is flow-through (no output register).

LBO

Linear Burst

Order

I

LOW

Burst order selection input. When LBO is high the Interleaved burst sequence is

selected. When LBO is low the Linear burst sequence is selected. LBO is a static

DC input.

OE

Output Enable

I

LOW

Asynchronous output enable. OE must be low to read data from the 71V547.

When OE is high the I/O pins are in a high-impedance state. OE does not need

to be actively controlled for read and write cycles. In normal operation, OE can be

tied low.

Power Supply

N/A

N/A

3.3V power supply input.

Ground

N/A

N/A

Ground pin.

3822 tbl 02