Electronic Components Datasheet Search |
|
71V2556XS150PFGI8 Datasheet(PDF) 1 Page - Integrated Device Technology |
|
71V2556XS150PFGI8 Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 25 page APRIL 2011 DSC-4875/12 1 ©2011 Integrated Device Technology, Inc. Pin Description Summary Description The IDT71V2556 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit) synchronous SRAM. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, they have been given the name ZBTTM, or Zero Bus Turnaround. Features ◆ ◆ ◆ ◆ ◆ 128K x 36 memory configurations ◆ ◆ ◆ ◆ ◆ Supports high performance system speed - 166 MHz (3.5 ns Clock-to-Data Access) ◆ ◆ ◆ ◆ ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ ◆ ◆ ◆ ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ ◆ ◆ ◆ ◆ Single R/W (READ/WRITE) control pin ◆ ◆ ◆ ◆ ◆ Positive clock-edge triggered address, data, and control signal registers for fully pipelined applications ◆ ◆ ◆ ◆ ◆ 4-word burst capability (interleaved or linear) ◆ ◆ ◆ ◆ ◆ Individual byte write (BW1 - BW4) control (May tie active) ◆ ◆ ◆ ◆ ◆ Three chip enables for simple depth expansion ◆ ◆ ◆ ◆ ◆ 3.3V power supply (±5%), 2.5V I/O Supply (VDDQ) ◆ ◆ ◆ ◆ ◆ Optional - Boundary Scan JTAG Interface (IEEE 1149.1 complaint) ◆ ◆ ◆ ◆ ◆ Packaged in a JEDEC standard 100-pin plastic thin quad flatpack (TQFP) and 119 ball grid array (BGA) A0 A - 6 1 s t u p n I s s e r d d At u p n Is u o n o r h c n y S E C 1 E C , 2 , E C 2 s e l b a n E p i h Ct u p n Is u o n o r h c n y S E O e l b a n E t u p t u Ot u p n Is u o n o r h c n y s A / R W l a n g i S e ti r W / d a e Rt u p n Is u o n o r h c n y S N E C e l b a n E k c o l Ct u p n Is u o n o r h c n y S W B 1, W B 2, W B 3, W B 4 s t c e l e S e ti r W e t y B l a u d i v i d n It u p n Is u o n o r h c n y S K L Ck c o l Ct u p n IA / N / V D A D L s s e r d d a w e n d a o L / s s e r d d a t s r u b e c n a v d At u p n Is u o n o r h c n y S O B L r e d r O t s r u B d e v a e lr e t n I / r a e n i Lt u p n Ic it a t S S M Tt c e l e S e d o M t s e Tt u p n Is u o n o r h c n y S I D Tt u p n I a t a D t s e Tt u p n Is u o n o r h c n y S K C Tk c o l C t s e Tt u p n IA / N O D Tt u p t u O a t a D t s e Tt u p t u Os u o n o r h c n y S T S R T )l a n o it p O ( t e s e R G A T Jt u p n Is u o n o r h c n y s A Z Ze d o M p e e l St u p n Is u o n o r h c n y S O /I 0 O /I - 1 3 O /I , 1 P O /I - 4 P t u p t u O / t u p n I a t a DO /Is u o n o r h c n y S V D D V , Q D D r e w o P O /I ,r e w o P e r o Cy l p p u Sc it a t S V S S d n u o r Gy l p p u Sc it a t S 1 0 l b t 5 7 8 4 IDT71V2556S/XS IDT71V2556SA/XSA 128K x 36 3.3V Synchronous ZBT™ SRAMs 2.5V I/O, Burst Counter Pipelined Outputs AddressandcontrolsignalsareappliedtotheSRAMduringoneclock cycle, and two cycles later the associated data cycle occurs, be it read or write. The IDT71V2556 contains data I/O, address and control signal registers.Outputenableistheonlyasynchronoussignalandcanbeused todisabletheoutputsatanygiventime. AClockEnable(CEN)pinallowsoperationoftheIDT71V2556tobe suspended as long as necessary. All synchronous inputs are ignored when(CEN)ishighandtheinternaldeviceregisterswillholdtheirprevious values. Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser to deselect the device when desired. If any one of these three are not assertedwhenADV/LDislow,nonewmemoryoperationcanbeinitiated. However,anypendingdatatransfers(readsorwrites)willbecompleted. The data bus will tri-state two cycles after chip is deselected or a write is initiated. TheIDT71V2556hasanon-chipburstcounter.Intheburstmode,the IDT71V2556 can provide four cycles of data for a single address presentedtotheSRAM.Theorderoftheburstsequenceisdefinedbythe LBO inputpin.TheLBOpinselectsbetweenlinearandinterleavedburst sequence. The ADV/LD signal is used to load a new external address (ADV/LD = LOW) or increment the internal burst counter (ADV/LD = HIGH). TheIDT71V2556SRAMsutilizeIDT's latesthigh-performanceCMOS processandarepackagedinaJEDECstandard14mmx20mm100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA). |
Similar Part No. - 71V2556XS150PFGI8 |
|
Similar Description - 71V2556XS150PFGI8 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |