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IDT723631 Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT723631 Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 20 page 1 MARCH 2014 DSC-2023/8 ©2014 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. CMOS SyncFIFO™ 512 x 36 1,024 x 36 2,048 x 36 IDT723631 IDT723641 IDT723651 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES FEATURES: ••••• Storage capacity: IDT723631 - 512 x 36 IDT723641 - 1,024 x 36 IDT723651 - 2,048 x 36 ••••• Supports clock frequencies up to 67 MHz ••••• Fast access times of 11ns ••••• Free-running CLKA and CLKB can be asynchronous or coinci- dent (permits simultaneous reading and writing of data on a single clock edge) ••••• Clocked FIFO buffering data from Port A to Port B ••••• Synchronous read retransmit capability ••••• Mailbox register in each direction ••••• Programmable Almost-Full and Almost-Empty flags ••••• Microprocessor interface control logic ••••• Input Ready (IR) and Almost-Full (AF) flags synchronized by CLKA ••••• Output Ready (OR) and Almost-Empty (AE) flags synchronized by CLKB ••••• Available in space-saving 120-pin thin quad flat package (TQFP) ••••• Green parts available, see ordering information DESCRIPTION: The IDT723631/723641/723651 is a monolithic high-speed, low-power, CMOS clocked FIFO memory. It supports clock frequencies up to 67 MHz and has read access times as fast as 11ns. The 512/1,024/2,048 x 36 dual-port SRAM FIFO buffers data from port A to Port B. The FIFO memory has retransmit capability, which allows previously read data to be ac- cessed again. The FIFO has flags to indicate empty and full conditions and two programmable flags (Almost-Full and Almost-Empty) to indicate when a selected number of words is stored in memory. Communication between each port may take place with two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Two or more FUNCTIONAL BLOCK DIAGRAM Mail 1 Register CLKA CSA W/ RA ENA MBA Port-A Control Logic Reset Logic RST CLKB CSB W/RB ENB MBB Port-B Control Logic MBF1 OR AE B0 - B35 3023 drw01 Mail 2 Register Write Pointer Read Pointer Status Flag Logic MBF2 IR AF FS0/SD FS1/ SEN Flag Offset Registers A0 - A35 10 RTM RFM RAM ARRAY 512 x 36 1,024 x 36 2,048 x 36 36 |
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