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M21262G-12 Datasheet(PDF) 10 Page - M/A-COM Technology Solutions, Inc.

Part # M21262G-12
Description  Integrated loop filter and terminations
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Manufacturer  MA-COM [M/A-COM Technology Solutions, Inc.]
Direct Link  http://www.macomtech.com
Logo MA-COM - M/A-COM Technology Solutions, Inc.

M21262G-12 Datasheet(HTML) 10 Page - M/A-COM Technology Solutions, Inc.

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M21262-12
M/A-COM Technology Solutions Inc. (MACOM) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice.
Visit www.macom.com for additional data sheets and product information.
For further information and support please visit:
http://www.macom.com/support
5
CDR/Reclocker with 4:1 Input Multiplexer
Rev V3
1.1.8
Multifunction Pins Defined for Hardwired Mode
In the hardwired mode, a subset of options in the M21262 can be accessed with hardwired physical pins, as
defined in Table 1-5. The hardwired bit rates along with the default reference clock frequency are shown in
Table 1-5. Table 1-6 provides the default reference clock frequency associated with each hardwired data rate.
Table 1-5.
Multifunction Pins for Hardwired Mode
Pin
Name
Function
Description
MF0
Rate_Sel_0
Data rate selection
CDR/Reclocker data rate select (see Table 1-6 for description)
MF1
Rate_Sel_1
Data rate selection
CDR/Reclocker data rate select (see Table 1-6 for description)
MF2
Rate_Sel_2
Data rate selection
CDR/Reclocker data rate select (see Table 1-6 for description)
MF3
Rate_Sel_3
Data rate selection
CDR/Reclocker data rate select (see Table 1-6 for description)
MF4
xPre_Emp_En
Pre-emphasis control
L = Pre-emphasis enable
H = Pre-emphasis disable
MF5
RSVD_Int_0
MACOM internal
Internal use only
MF6
RSVD_Int_1
MACOM internal
Internal use only
MF7
xPol_Flip_En
Data polarity flip
L = Data polarity flip
H = Standard data polarity
MF8
Out_Level_[1:0]
Output level selection
00b: All outputs disabled
01b: 500 mV (CML)
10b: 900 mV (CML)
11b: 1200 mV (CML)
See Table 1-1 for the other output interface modes.
MF9
Output level selection
MF10
xEQ_En
Equalization control
L = Input equalization enabled
H = Input equalization disabled
MF11
xRCLK_BYP_En
CDR/RCLK bypass control
L = CDR/Reclocker bypassed and powered down
H = CDR/Reclocker enabled
Table 1-6.
Hardwired Bit Rates and Associated Reference Frequencies
Pins
MF[3:0]
Application
Bit Rate (Mbps)
Reference Frequency (MHz)
0000
2 x HD-SDI
2967/2970
12.0
0001
HD-SDI
1485 /1483.5
12.0
0010
2 x SD-SDI
540
12.0
0011
Progressive Scan Video
360
12.0
0100
SD-SDI
270
12.0
0101
Legacy Comp Video
177
12.0
0110
Legacy Comp Video
143
12.0


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