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709279S15PFG8 Datasheet(PDF) 10 Page - Integrated Device Technology |
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709279S15PFG8 Datasheet(HTML) 10 Page - Integrated Device Technology |
10 / 17 page 6.42 IDT709279/69S/L Preliminary High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges 10 Timing Waveform with Port-to-Port Flow-Through Read(1,2,3,5) DATAIN "A" CLK "B" R/ W "B" ADDRESS "A" R/ W "A" CLK "A" ADDRESS "B" NO MATCH MATCH NO MATCH MATCH VALID tCWDD tCD1 tDC DATAOUT "B" 3243 drw 10 VALID VALID tSW tHW tSA tHA tSD tHD tHW tCD1 tCCS tDC tSA tSW tHA (4) (4) NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 3. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to. 4. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case. 5. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A". |
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