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709369L12PFGI Datasheet(PDF) 2 Page - Integrated Device Technology |
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709369L12PFGI Datasheet(HTML) 2 Page - Integrated Device Technology |
2 / 16 page 6.42 IDT709379/69L High-Speed 32/16K x 18 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges 2 INDEX 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 9897 96 95 94 93 9291 90 89 8887 8685 8483 82 8180 7978 77 76 FT/PIPER OER R/ WR CNTRSTR CE1R CE0R GND A12R A13R A11R A10R A9R A14R(1) I/O11R I/O12R I/O13R I/O14R I/O15R GND UBR LBR 4845 drw 02 I/O15L FT/PIPEL OEL R/ WL CNTRSTL CE1L CE0L VCC A14L(1) A13L A12L A11L A10L A9L I/O10L I/O11L I/O12L I/O13L I/O14L UBL LBL GND A8R 709379/69PF PN100(5) 100-Pin TQFP Top View(6) NC NC I/O16R I/O17R I/O17L I/O16L . Pin Configurations(1,2,3) NOTES: 1. A14x is a NC for IDT709369. 2. All VCC pins must be connected to power supply. 3. All GND pins must be connected to ground. 4. Package body is approximately 14mm x 14mm x 1.4mm 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking. Description The IDT709379/69 is a high-speed 32/16K x 18 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allowsimultaneousaccessofanyaddressfrombothports.Registerson control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. Withaninputdataregister,theIDT709379/69hasbeenoptimizedfor applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using CMOS high-performance technology, these devices typically operate on only 1.2W of power. |
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