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C8051F020 Datasheet(PDF) 2 Page - Silicon Laboratories |
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C8051F020 Datasheet(HTML) 2 Page - Silicon Laboratories |
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2 / 16 page  AN131 2 Rev. 1.3 Example code showing how to initialize the PLL is included at the end of this note. Please refer to the Oscillators section of the C8051F12x datasheet for step-by-step instructions for initializing the PLL. SFR Paging The C8051F12x series implements a ‘paged’ SFR scheme which greatly expands the number of avail- able SFR addresses. This SFR address expansion provides support for more peripherals and gives the programmer added flexibility. For example, Port 4 through Port 7 now occupy bit-addressable SFR locations. Reading and Writing to SFR Registers To correctly read or write to an SFR, the SFRPAGE register must be set to the correct SFR page. The SFRPAGE register is accessible from all SFR pages. When changing SFR pages, it is recom- mended to use the named constants in Figure 1 instead of assigning the actual SFR page number. These are defined in the supplied ‘C8051F120.h’ and ‘C8051F120.inc’ files. This enhances code readability and reduces the porting effort to future platforms. SFR Paging and Interrupts By default, SFR page switching is handled auto- matically by hardware when an interrupt occurs. Upon entry into an interrupt service routine (ISR), the SFRPAGE register will automatically switch to the SFR page containing the flag bit that caused the interrupt. Upon exit of the ISR, the SFR page is automatically restored to the SFR page in use prior to the interrupt. For more information on SFR paging, please see the CIP-51 section of the C8051F12x datasheet. Figure 1. SFR Page Names SFR Page Names SFR Page Number LEGACY_PAGE TIMER01_PAGE UART0_PAGE SPI0_PAGE EMI0_PAGE ADC0_PAGE SMB0_PAGE TMR2_PAGE DAC0_PAGE PCA0_PAGE 0x00 CPT0_PAGE UART1_PAGE TMR3_PAGE DAC1_PAGE 0x01 CPT1_PAGE ADC2_PAGE TMR4_PAGE 0x02 CONFIG_PAGE PLL0_PAGE 0x0F Figure 1. SFR Page Names SFR Page Names SFR Page Number |
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