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C8051F022 Datasheet(PDF) 3 Page - Silicon Laboratories |
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C8051F022 Datasheet(HTML) 3 Page - Silicon Laboratories |
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3 / 16 page  AN131 Rev. 1.3 3 Code Banking The C8051F12x series supports code banking for projects requiring greater than 64KB of FLASH. All code bank switching is handled by writing to the PSBANK register. Projects smaller than 64KB can leave the PSBANK register at its default set- ting which provides a 64KB linear address space. When code banking is used, the common area (FLASH addresses between 0x0000 to 0x7FFF) is always available regardless of the PSBANK regis- ter. The address space from 0x8000 to 0xFFFF can be mapped to one of 4 physical 32KB banks of FLASH, depending on the value of PSBANK. Please see the FLASH and CIP-51 sections of the C8051F12x datasheet for more detailed informa- tion on the code banking architecture. For larger projects, the user has the option of manu- ally handling the bank switching in software or set- ting up a code banked project and allowing the linker to manage the bank switching. The advan- tages and disadvantages of both methods are dis- cussed below. User-Managed Bank Switching for Data Intensive Projects User-managed bank switching is useful for projects that have less than 64KB of executable code but need to store large amounts of data in FLASH. In this situation, the common area and Bank 1 are used for program memory while Bank 2 and Bank 3 are used for data storage. The project does not need to be set up for code banking. Bank selection for constant data (accessed via MOVC and MOVX instructions) is handled inde- pendently of bank selection for instruction fetches (normal code execution). The IFBANK bits, which control the instruction fetch operations, should be left at their reset values, targeting Bank 1. The COBANK bits, which control constant operations, should be set to select the desired bank before read- ing, writing, or erasing FLASH. If an interrupt changes the COBANK bits, it should restore them prior to ISR exit. The PSBANK register is not restored by hardware and should be managed by software. Project-Managed Bank Switching Allowing the linker to manage code banking is a must for projects that have more than 64KB of exe- cutable program code. It allows functions in one bank to call functions located in another bank with- out the programmer having to worry about bank switching. There is a restriction, however. Constant code variables and tables must be located in the common area or in the bank containing the function which accesses them. For more information on this topic and for step-by-step instructions on how to set up a code-banked project, please refer to AN130 on the Silicon Labs website. Caching The ‘F12x family of devices possess a branch tar- get buffer and a pre-fetch engine which provide optimal performance for a broad range of circum- stances. In most applications, the cache control reg- isters should be left in their reset states. Please refer to the C8051F12x datasheet for more information on the cache controller. Interrupt Vector Table The interrupt vector table in the ‘F12x is different from the ‘F02x interrupt vector table. External Interrupt 6, External Interrupt 7, and the External Crystal OSC Ready interrupts have been removed. The ADC2 Window Comparator interrupt has been added as interrupt 17 (0x008B) and the ADC1 End of Conversion interrupt has been renamed to ADC2 End of Conversion and moved to interrupt 18 |
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