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C8051F127 Datasheet(PDF) 5 Page - Silicon Laboratories |
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C8051F127 Datasheet(HTML) 5 Page - Silicon Laboratories |
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5 / 16 page  AN131 Rev. 1.3 5 tors equivalent to the speed and power consump- tion of the ‘F02x comparators. Note that SFRPAGE should be set to CPT0_PAGE or CPT1_PAGE when reading or writing comparator registers. Reset Sources Forcing a power-on reset via software in the ‘F12x is accomplished by writing a ‘1’ to PINRSF (bit 0 in the RSTSRC register) instead of PORSF (bit 1 in the RSTSRC register) as in the ‘F02x. PORSF in the ‘F12x has been changed from read/write to read only. The instruction prefetch engine must be enabled in order to disable the watchdog timer. The instruction prefetch engine is enabled by default upon reset. Note that SFRPAGE should be set to LEGA- CY_PAGE before any reads or writes to RSTSRC. Oscillators Please see the “Clocking” section of this docu- ment. FLASH Memory Please see the “Code Banking” section of this doc- ument. External Memory Interface (EMIF) The external memory interface on the ‘F12x is identical to the one on the ‘F02x. However, because the ‘F12x devices can operate significantly faster than the ‘F02x devices, be sure to check the timing requirements for devices on the bus. Note that SFRPAGE should be set to LEGACY_PAGE before any reads or writes to EMIF registers. Port Input/Output Port 4 through Port 7 now occupy bit addressable SFR locations on the ‘F12x. Separate PnMDOUT registers have been added for each port and the P74OUT register has been removed. Note that SFRPAGE should be set to CONFIG_PAGE when reading or writing to Port 4 through Port 7 and the port input and output mode (PnMDIN and PnMD- OUT) registers. The CEX5 and CNVSTR2 signals have been added as Crossbar inputs. The CNVSTR signal has been renamed to CNVSTR0. If the application does not use any of the newly added or renamed signals, then the Crossbar configuration code will not need modification. Note that SFRPAGE should be set to CONFIG_PAGE before reading or writing to cross- bar registers. System Management Bus/I2C Bus (SMBUS0) The formula for calculating SMB0CR has changed on the ‘F12x. Please refer to the System Manage- ment Bus section of the C8051F12x datasheet for more information about SMBUS0. Note that SFRPAGE should be set to SMB0_PAGE before any reads or writes to SMBUS0 registers. Enhanced Serial Peripheral Interface (SPI0) The ‘F12x series features an enhanced Serial Peripheral Interface. The enhanced SPI0 supports double buffered transmits and multi-byte transac- tions when in slave mode. Also, it can now operate in 3-wire or 4-wire mode making the NSS signal optional. The SPI0 configuration registers have changed on the ‘F12x. For more information on the enhanced SPI0, please refer to the C8051F12x datasheet. Note that SFRPAGE should be set to SPI0_PAGE before any reads or writes to SPI0 reg- isters. UART For UART0 on the ‘F12x, timer selection for baud rate generation has been moved to the newly added SSTA0 register. UART0 now supports using |
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