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MC145190F Datasheet(PDF) 10 Page - Motorola, Inc |
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MC145190F Datasheet(HTML) 10 Page - Motorola, Inc |
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10 / 24 page  MC145190 •MC145191 MOTOROLA 10 A counter, and N counter. The divide ratio between the fin in- put and the fV signal is N × 64 + A. N is the divide ratio of the N counter and A is the divide ratio of the A counter. These ratios are determined by bits loaded into the A register. See Figure 16. The maximum frequency at which the phase detectors operate is 2 MHz. Therefore, the frequency of fV should not exceed 2 MHz. If A23 = low and A22 = high, OUTPUT A is configured as Data Out. This signal is the serial output of the 24–1/2–stage shift register. The bit stream is shifted out on the high–to–low transition of the CLK input. Upon power up, OUTPUT A is automatically configured as Data Out to facilitate cascading devices. If A23 = A22 = low, OUTPUT A is configured as Port. This signal is a general–purpose digital output which may be used as an MCU port expander. This signal is low when the Port bit (C1) of the C register is low, and high when the Port bit is high. OUTPUT B Open–Drain Digital Output (Pin 15) This signal is a general–purpose digital output which may be used as an MCU port expander. This signal is low when the Out B bit (C0) of the C register is low. When the Out B bit is high, OUTPUT B assumes the high–imped- ance state. OUTPUT B may be pulled up through an external resistor or active circuitry to any voltage less than or equal to the potential of the VPD pin. Note: the maximum voltage allowed on the VPD pin is 9.5 V for the MC145190 and 5.5 V for the MC145191. Upon power–up, power–on reset circuitry forces OUTPUT B to a low level. REFERENCE PINS REFin and REFout Reference Input and Reference Output (Pins 20 and 1) Configurable pins for a Crystal or an External Reference. This pair of pins can be configured in one of two modes: the crystal mode or the reference mode. Bits R13, R14, and R15 in the R register control the modes as shown in Figure 17. In crystal mode, these pins form a reference oscillator when connected to terminals of an external parallel–reso- nant crystal. Frequency–setting capacitors of appropriate values as recommended by the crystal supplier are con- nected from each of the two pins to ground (up to a maximum of 30 pF each, including stray capacitance). An external re- sistor of 1 M Ω to 15 MΩ is connected directly across the pins to ensure linear operation of the amplifier. The device is de- signed to operate with crystals up to 15 MHz; the required connections are shown in Figure 9. To turn on the oscillator, bits R15, R14, and R13 must have an octal value of one (001 in binary, respectively). This is the active–crystal mode shown in Figure 17. In this mode, the crystal oscillator runs and the R Counter divides the crystal frequency, unless the part is in standby. If the part is placed in standby via the C register, the oscillator runs, but the R counter is stopped. However, if bits R15 to R13 have a value of 0, the oscillator is stopped, which saves additional power. This is the shut– down crystal mode (shown in Figure 17) and can be engaged whether in standby or not. In the reference mode, REFin (Pin 20) accepts a signal up to 27 MHz from an external reference oscillator, such as a TCXO. A signal swinging from at least the VIL to VIH levels listed in the Electrical Characteristics table may be directly coupled to the pin. If the signal is less than this level, ac cou- pling must be used as shown in Figure 8. Due to an on– board resistor which is engaged in the reference modes, an external biasing resistor tied between REFin and REFout is not required. With the reference mode, the REFout pin is configured as the output of a divider. As an example, if bits R15, R14, and R13 have an octal value of seven, the frequency at REFout is the REFin frequency divided by 16. In addition, Figure 17 shows how to obtain ratios of eight, four, and two. A ratio of one–to–one can be obtained with an octal value of three. Upon power up, a ratio of eight is automatically initialized. The maximum frequency capability of the REFout pin is 10 MHz. Therefore, for REFin frequencies above 10 MHz, the one–to–one ratio may not be used. Likewise, for REFin frequencies above 20 MHz, the ratio must be more than two. If REFout is unused, an octal value of two should be used for R15, R14, and R13 and the REFout pin should be floated. A value of two allows REFin to be functional while disabling REFout, which minimizes dynamic power consumption and electromagnetic interference (EMI). LOOP PINS fin and fin Frequency Inputs (Pins 11 and 10) These pins are frequency inputs from the VCO. These pins feed the on–board RF amplifier which drives the 64/65 pres- caler. These inputs may be fed differentially. However, they usually are used in a single–ended configuration (shown in Figure 7). Note that fin is driven while fin must be tied to ground via a capacitor. Motorola does not recommend driving fin while terminating fin because this configuration is not tested for sensitivity. The sensitivity is dependent on the frequency as shown in the Loop Specifications table. PDout Single–Ended Phase/Frequency Detector Output (Pin 6) This is a three–state current–source/sink output for use as a loop error signal when combined with an external low–pass filter. The phase/frequency detector is characterized by a lin- ear transfer function (no dead zone). The operation of the phase/frequency detector is described below and is shown in Figure 18. POL bit (C7) in the C register = low (see Figure 15) Frequency of fV > fR or Phase of fV Leading fR: current– sinking pulses from a floating state Frequency of fV < fR or Phase of fV Lagging fR: current– sourcing pulses from a floating state Frequency and Phase of fV = fR: essentially a floating state; voltage at pin determined by loop filter POL bit (C7) = high Frequency of fV > fR or Phase of fV Leading fR: current– sourcing pulses from a floating state Frequency of fV < fR or Phase of fV Lagging fR: current– sinking pulses from a floating state Frequency and Phase of fV = fR: essentially a floating state; voltage at pin determined by loop filter This output can be enabled, disabled, and inverted via the C register. If desired, PDout can be forced to the floating state by utilization of the disable feature in the C register (bit C6). This is a patented feature. Similarly, PDout is forced to the |
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