2010-04-13

6

SCDQ5541P/Q/R, SCDQ5542P/Q/R, SCDQ5543P/Q/R, SCDQ5544P/Q/R

Close Up of Data “Write” Cycle

Device Timing

Write Cycle Timing

(over operating temperature range, V

Symbol

Description

Min.

Max.

Units

T

LDS

Load Setup Time

50

—

ns

T

DS

Data Setup Time

50

—

ns

T

SDCLK

Clock Period

200

—

ns

T

SDCW

(HI or LOW)

Clock Width

70

—

ns

T

LDH

Load Hold Time

0

—

ns

T

DH

Data Hold Time

25

—

ns

T

WR

Total Write Time

2.25

—

µs

T

BL

Time Between Writes

600

—

ns

T

RST

Reset Active Time

600

—

ns

Notes:

1.

T

2.

Data is shifted into the display’s 8 bit shift register on the positive going edge of the SDCLK.

3.

Shift register data is evaluated when Load goes high.

LOAD

LOAD

DATA

DATA

SDCLK

SDCLK

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

D0

D0

BL

T

WR

T

OR