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MC100ELT22DTR2 Datasheet(PDF) 1 Page - ON Semiconductor |
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MC100ELT22DTR2 Datasheet(HTML) 1 Page - ON Semiconductor |
1 / 8 page © Semiconductor Components Industries, LLC, 2000 October, 2000 – Rev. 4 1 Publication Order Number: MC10ELT22/D MC10ELT22, MC100ELT22 5VDual TTL to Differential PECL Translator The MC10ELT/100ELT22 is a dual TTL to differential PECL translator. Because PECL (Positive ECL) levels are used only +5 V and ground are required. The small outline 8-lead package and the low skew, dual gate design of the ELT22 makes it ideal for applications which require the translation of a clock and a data signal. • 1.2 ns Typical Propagation Delay • <300 ps Typical Output to Output Skew • PNP TTL Inputs for Minimal Loading • Flow Through Pinouts • ESD Protection: >2 KV HBM, >200 V MM • Operating Range: V CC= 4.75 V to 5.25 V with GND= 0 V • No Internal Input Pulldown Resistors • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test • Moisture Sensitivity Level 1 For Additional Information, see Application Note AND8003/D • Flammability Rating: UL–94 code V–0 @ 1/8”, Oxygen Index 28 to 34 • Transistor Count = 51 devices 1 2 3 45 6 7 8 D0 GND VCC LOGIC DIAGRAM AND PINOUT ASSIGNMENT Q0 D1 Q1 Q1 Q0 PECL TTL PIN FUNCTION Qn, Qn PECL Differential Outputs* Dn TTL Inputs VCC Positive Supply GND Ground PIN DESCRIPTION * Output state undetermined when inputs are open. http://onsemi.com Device Package Shipping ORDERING INFORMATION MC10ELT22D SO–8 98 Units/Rail MC10ELT22DR2 SO–8 2500 Tape & Reel MC100ELT22D SO–8 98 Units/Rail MC100ELT22DR2 SO–8 2500 Tape & Reel MC10ELT22DT TSSOP–8 98 Units/Rail MC10ELT22DTR2 TSSOP–8 2500 Tape & Reel MC100ELT22DT TSSOP–8 98 Units/Rail MC100ELT22DTR2 TSSOP–8 2500 Tape & Reel L = Wafer Lot Y = Year W = Work Week *For additional information, see Application Note AND8002/D H = MC10 K = MC100 A = Assembly Location SO–8 D SUFFIX CASE 751 MARKING DIAGRAMS* TSSOP–8 DT SUFFIX CASE 948R 1 8 1 8 ALYW KLT22 1 8 HLT22 1 8 ALYW ALYW HT22 1 8 ALYW KT22 1 8 |
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