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MK2308S-1 Datasheet(PDF) 4 Page - Integrated Circuit Systems

Part # MK2308S-1
Description  3.3 VOLT ZERO DELAY, LOW SKEW BUFFER
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Manufacturer  ICST [Integrated Circuit Systems]
Direct Link  http://www.icst.com
Logo ICST - Integrated Circuit Systems

MK2308S-1 Datasheet(HTML) 4 Page - Integrated Circuit Systems

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3.3 VOLT ZERO DELAY, LOW SKEW BUFFER
MDS 2308-1 A
4
Revision 100603
In te gr ated Circuit Systems 5 25 Race Stree t , San Jose, CA 951 26 te l (40 8 ) 2 95-98 00 www.icst .com
MK2308-1
DC Electrical Characteristics
VDD=3.3 V ±10%, Ambient temperature -40 to +85
°C(Industrial), (0-70°C Commercial),
AC Electrical Characteristics
VDD = 3.3 V ±10%, Ambient Temperature -40 to +85
°C(Industrial), (0-70°C Commercial)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Operating Voltage
VDD
3.0
3.6
V
Input High Voltage
VIH
2V
Input Low Voltage
VIL
0.8
V
Input Low Current
IIL
VIN = 0V
50
µA
Input High Current
IIH
VIN = VDD
100
µA
Output High Voltage
VOH
IOH = -12 mA
2.4
V
Output Low Voltage
VOL
IOL = 12 mA
0.4
V
Output High Voltage,
CMOS level
VOH
IOH = -4 mA
VDD-0.4
V
Operating Supply Current
IDD
No Load, S2 = 1, S1 = 1,
Note 1
70
mA
Power Down Supply
Current
IDDPD
CLKIN = 0, S2 = 0, S1 = 1
12
µA
CLKIN = 0, Note 2
12
µA
Short Circuit Current
IOS
Each output
±50
mA
Input Capacitance
CIN
S2, S1, FBIN
5
pF
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Input Clock Frequency
fIN
See table on page 2
10
133
MHz
Output Clock Frequency
See table on page 2
10
133
MHz
Output Rise Time
tOR
0.8 to 2.0 V, CL=30 pF
1.5
ns
Output Fall Time
tOF
2.0 to 0.8 V, CL=30 pF
1.25
ns
Output Clock Duty Cycle
tDC
measured at VDD/2
45
50
55
%
Device to Device Skew
rising edges at VDD/2
700
ps
Output to Output Skew
rising edges at VDD/2
200
ps
Input to Output Skew
rising edges at VDD/2, FBIN to
CLKA4, S1 = 1, S0 = 1, Note 1
±250
ps
Maximum Absolute Jitter
CL=15 pF, measured at 66.67M
130
ps


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