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IDT71V124SA-TY Datasheet(PDF) 1 Page - ATMEL Corporation |
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IDT71V124SA-TY Datasheet(HTML) 1 Page - ATMEL Corporation |
1 / 17 page 1 Table Of Contents TABLE OF CONTENTS.............................................................................1 STK503 USER GUIDE.....................................................................................................2 INTRODUCTION...............................................................................................................2 Features.......................................................................................................................................2 Known Issues.......................................................................................................................3 Getting Started ....................................................................................................................4 Hardware overview ...............................................................................................................................4 Mounting the STK503 ..........................................................................................................................5 Placing the AVR in the ZIF socket......................................................................................................5 Programming the AVR....................................................................................................7 In-System Programming (ISP) ............................................................................................................7 High-Voltage Parallel Programming (HVPP) ....................................................................................8 JTAG Programming ...................................................................................................................9 STK503 Clock Sources................................................................................................10 The XTAL switch.................................................................................................................................10 The TOSC switch................................................................................................................................11 The External Memory Interface...............................................................................11 SRAM footprint ....................................................................................................................................11 Address latch.......................................................................................................................................12 High address jumpers ........................................................................................................................12 RS-232 Driver ....................................................................................................................13 Debugging with JTAGICE mkII ...............................................................................14 Connecting the JTAGICE ..................................................................................................................14 Troubleshooting Guide.................................................................................................15 Programming problems......................................................................................................................15 General problems.....................................................................................................................15 Problem .......................................................................................................................................15 Appendix ...............................................................................................................................16 Port Connectors ..................................................................................................................................16 SRAM ...................................................................................................................................................16 Schematic and layout ..............................................................................................................17 |
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