ISL99125B, ISL99135B

10

FN8848.4

January 24, 2017

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Operation

The ISL99125B, ISL99135B are optimized driver and power

stage solutions for high-density synchronous DC/DC power

conversion. The ISL99125B and ISL99135B include a

high-performance driver, integrated Schottky bootstrap diode,

and MOSFET pair optimized for high switching frequency buck

voltage regulators. The ISL99125B, ISL99135B include a driver

with advanced power management features that allow direct

control of the lower MOSFET and diode emulation as well as

IMVP8 PS4 shutdown mode.

Power-On Reset (POR)

2.95V (typically), operation of the driver is disabled.

Shoot-Through Protection

function is activated and both GH and GL are held active low (off).

“Electrical Specifications” on page 6) the PWM and FCCM signals

are used to control both high-side and low-side MOSFETs.

The rising edge on PWM initiates the turn-off of the lower

MOSFET. Adaptive shoot-through circuitry monitors the GL

voltage and determines a safe time for the upper MOSFET to

turn-on. This prevents the MOSFETs from conducting

simultaneously.

The falling PWM transition causes the upper FET to turn off and

the lower FET to turn on. Adaptive shoot-through circuitry

monitors the GH to SW voltage to determine a safe time for the

low-side MOSFET turn-on. This prevents the MOSFETs from

conducting simultaneously.

Should the driver have no bias voltage applied and be unable to

actively hold the MOSFETs off, an integrated 20kΩ resistor from

the upper MOSFET gate-to-source will aid in keeping the device in

its off state. This can be especially critical in applications where

the input voltage rises prior to the ISL99125B and ISL99135B

Tri-State PWM Input

The ISL99125B and ISL99135B supports a tri-level input on the

PWM pin. Should the pin be pulled into and remain in the tri-state

window for a set hold-off time, the driver will force both MOSFETs

to their off states. When the PWM signal moves outside the

shutdown window, the driver immediately resumes driving the

MOSFETs according to the PWM commands.

This feature is utilized by Intersil PWM controllers as a method of

forcing both MOSFETs off. Should the PWM input be left floating,

the pin will be pulled into the tri-state window internally and force

both MOSFETs to a safe off state. The ISL99125B and

ISL99135B’s tri-state levels are compatible with 5.0V PWM logic.

FCCM Operation

Diode emulation allows for higher converter efficiency under light

load situations. With diode emulation active (FCCM pulled low),

the ISL99125B and ISL99135B will detect the zero current

crossing of the output inductor and turn off the low-side gate

after the minimum LGATE ON-time of 350ns expires. This

ensures that Discontinuous Conduction Mode (DCM) is achieved

to minimize losses. Diode emulation is asynchronous to the PWM

signal. Therefore, the ISL99125B and ISL99135B will respond to

the FCCM input immediately after it changes state. This

operation is compatible with the ISL95825 VR12.5/12.6

controller for diode emulation operation and the ISL68201

digital hybrid controller for PFM operation, significantly improving

light-load efficiency.

Furthermore, compared to conventional drivers with FCCM input,

the ISL99125B and ISL99135B enters shutdown operation of

both the high-side and low-side MOSFET when the FCCM pin

enters its tri-state window. This mode reduces the total bias

current to 3µA and significantly reduces the power consumption

at standby mode, which is required to support Intel IMVP8 PS4

shutdown operation and compatible with ISL95855, ISL95857,

ISL95859, and ISL95829 IMVP8 controllers.

For incompatible controllers without the FCCM output pin such as

ISL6398, ISL637x, ISL633x, and ISL636x, the ISL99125B and

Bootstrap Function

The ISL99125B and ISL99135B features an internal bootstrap

Schottky diode. A high quality ceramic capacitor should be

placed in close proximity across BOOT and PHASE pins. The

bootstrap capacitor can range between 0.1µF~0.22µF/X5R~X7R

for normal buck switching applications.

PCB Layout Considerations

Proper PCB layout will reduce noise coupling to other circuits,

improve thermal performance and maximize the efficiency. The

following is meant to lead to an optimized layout:

• Place multiple 10µF or greater ceramic capacitors directly at

the device between VIN and PGND as indicated in Figure 20.

This is the most critical decoupling and reduced parasitic

inductance in the power switching loop. This will reduce overall

electrical stress on the device as well as reduce coupling to

PWM

GH

FCCM

5V

5V

2.5V

FIGURE 19. PS4 EXIT TIMING DIAGRAM