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MCM32A932 Datasheet(PDF) 9 Page - Motorola, Inc |
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MCM32A932 Datasheet(HTML) 9 Page - Motorola, Inc |
9 / 12 page MCM32A732/764 •MCM32A832/864•MCM32A932/964 9 MOTOROLA FAST SRAM WRITE CYCLE 2 (E Controlled, See Notes 1 and 2) Data Tag/Valid Dirty Parameter Symbol Min Max Min Max Min Max Unit Notes Write Cycle Time tAVAV 30 — 30 — 30 — ns 4 Address Setup Time (A4 – A5) (A6 – A19) tAVEL 2 10 — — — 2 — — — 10 — — ns Address Valid to End of Write tAVEH 20 — 10 — 20 — ns Write Pulse Width tELEH, tELWH 15 — 10 — 15 — ns Data Setup to Write Time tDVEH 8 — 6 — 8 — ns Data Hold from Write Time tEHDX 0 — 0 — 0 — ns Write Recovery Time tEHAX 0 — 0 — 0 — ns NOTES: 1. A write occurs during the overlap of E low and W low. 2. E = Exx, ET; W = Wxx, WT, WA; G = GA, GB 3. All timings are referenced from the last valid address to the first transitioning address. 4. If E goes low coincident with or after W goes low, the output will remain in a high impedance state. 5. If E goes high coincident with or before W goes high, the output will remain in a high impedance state. WRITE CYCLE 2 (E Controlled, See Note 1) tEHDX tDVEH tEHAX tELWH tELEH tAVEL tAVEH DATA VALID tAVAV HIGH–Z A (ADDRESS) W (WRITE ENABLE) E (CHIP ENABLE) Q (DATA OUT) D (DATA IN) |
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