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CDP1854 Datasheet(PDF) 4 Page - Intersil Corporation |
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CDP1854 Datasheet(HTML) 4 Page - Intersil Corporation |
4 / 12 page 5-65 Dynamic Electrical Specifications tR, tF = 15ns, VIH = VDD, VIL = VSS, CL = 100pF, (See Figure 2) PARAMETER VDD (V) LIMITS UNITS -55oC, +25oC +125oC MIN MAX MIN MAX RECEIVER TIMING - MODE 1 Clock Period tCC 5 240 - 280 - ns 10 120 - 145 - ns Pulse Width Clock Low Level tCL 5 105 - 125 - ns 10 55 - 65 - ns Clock High Level tCH 5 135 - 155 - ns 10 65 - 80 - ns TPB tTT 5 125 - 165 - ns 10 70 - 80 - ns Setup Time Data Start Bit to Clock tDC 5 105 - 120 - ns 10 65 - 70 - ns Propagation Delay Time TPB to DATA AVAILABLE tTDA 5 - 295 - 340 ns 10 - 150 - 170 ns Clock to DATA AVAILABLE tCDA 5 - 305 - 355 ns 10 - 150 - 170 ns Clock to Overrun Error tCOE 5 - 305 - 330 ns 10 - 150 - 175 ns Clock to Parity Error tCPE 5 - 305 - 330 ns 10 - 150 - 175 ns Clock to Framing Error tCFE 5 - 280 - 330 ns 10 - 145 - 165 ns CDP1854A/3, CDP1854AC/3 |
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