TUSB2136 datasheet(5/50 Pages) TI

Part #	TUSB2136

Description	UNIVERSAL SERIAL BUS KEYBOARD HUB CONTROLLER

Download	50 Pages

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Manufacturer	TI [Texas Instruments]

Direct Link	http://www.ti.com

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5 / 50 page

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List of Illustrations

Figure

Title

Page

1–1 TUSB2136 Block Diagram

1–2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–1 MCU Memory Map (TUSB2136B)

2–1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–2 Reset Diagram

2–19

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–3 Pullup Resistor Connect/Disconnect Circuit

2–20

. . . . . . . . . . . . . . . . . . . . . . . . . .

2–4 Internal Vector Interrupt (INT0)2–23

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–5 P2[7:0] Input Port Interrupt Generation

2–23

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–1 Keyboard LED Connection

4–1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–2 Keyboard Matrix Scan Connection

4–2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–3 Partial Connection Bus Power Mode

4–2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–4 Upstream Connection (a) Non-Switching Power Mode (b) Switching

Power Mode

4–2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–5 Downstream Connection – Only One Port Shown

4–3

. . . . . . . . . . . . . . . . . . . . .

4–6 Reset Timing

4–3

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List of Tables

Table

Title

Page

2–1 XDATA Space

2–4

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–2 Memory Mapped Registers Summary (XDATA Range = FF80

→ FFFF)

2–5

. .

2–3 EDB and Buffer Allocations in XDATA

2–6

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–4 EDB Entries in RAM (n = 1 to 3)

2–7

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–5 Input/Output EDB-0 Registers

2–11

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–6 External Pins Mapping to S[3:0] in VIDSTA Register

2–19

. . . . . . . . . . . . . . . . . . .

2–7 8052 Interrupt Location Map

2–20

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–8 Vector Interrupt Values

2–22

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–1 GPIO Assignment for Matrix Scan and LED Drive

4–1

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