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U2350B-FP Datasheet(PDF) 3 Page - TEMIC Semiconductors |
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U2350B-FP Datasheet(HTML) 3 Page - TEMIC Semiconductors |
3 / 9 page U2350B-FP TELEFUNKEN Semiconductors Rev. A1, 29-May-96 3 (9) Pin Description 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 n.c. NTC 95 11409 Progr. Rosc Cosc Contr. LED1 LED2 OUT OUT– GND IContr. S1 VContr. +VS OUT+ Pin Symbol Function 1 LED1 LED output 1 2 LED2 LED output 2 3 n.c. Not connected 4 NTC Monitoring input 5 Progr. Tristate programing 6 Rosc Resistor for oscillator 7 Cosc Capacitor for oscillator 8 Contr. Control input 9 VContr. Voltage regulation input 10 S1 Switching output, output S1 11 IContr. Current regulation input 12 GND Ground 13 OUT– – supply for output stage 14 OUT Output 15 OUT+ + supply for output stage 16 +VS Supply voltage Supply, Pin 16 The internal voltage limiter in the U2350B enables a simple supply from the rectified line voltage. The supply voltage between Pin 16 (+VS) and Pin 12 (ground) is built up via R1 and is smoothed by C7. The typically 5 mA supply current is simultaneously used to operate the two LEDs D2, D3, which can both be bridged internally. The supply current therefore reaches Pin 16 either via LEDs or the internal switches (Vsat ≤ 1.2 V). Series resistor, R1, can be calculated as follows: R 1max + V Mmin –VSmax Itot whereas V Mmin + V mains –15% V Smax + maximum supply voltage Itot + I Smax ) I x I Smax + Max. current consumption of the IC Ix + Current consumption of the external components Here, C6 must be selected in this way that the voltage at C7 (figure 2) is not noticeably affected by the load in any mode of operation. For further information regarding mains power supply, refer to figures 6 and 7. Voltage Monitoring Whilst the operating voltage is being built up or reduced, uncontrolled output pulses of insufficient amplitude are suppressed by the internal monitoring circuit. The latch is also reset, the LED D2 (operating indicator) between Pin 2 and Pin 16 is switched off and the control input “Pin 8” is connected to ground via switch S3 and a 1 k W resistor. In connection with a switching hysteresis of approximately 2 V, this mode of operation guarantees fail-safe start-up each time the operating voltage is switched on, in the same way as after short mains interruptions. Connecting the control input Pin 8 with a capacitor can therefore make a soft start with rapid recovery possible. Pulse Width Control with Mains Voltage Compensation, Pins 8, 9, 10 Average value of the voltage over the load is controlled to an infinitely selectable value by the comparator Comp. 1 with hysteresis. The rectified mains voltage is divided by R3 and R4 and lead in Pin 10. The capacitor C1 is charged via R9 until the voltage V9, which is present at the inverting input of Comp. 1, is more positive than the control voltage V8 arriving at the non-inverting input via an impedance converter. During the charge time, which is dependent of the mains voltage, the pulse output is at high potential and the switching output Pin 10 is open. If V9 now becomes greater than V10, the output from Comp. 1 switches over the output stage logic via an AND gate. |
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