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LM3705YABPX-643 Datasheet(PDF) 2 Page - National Semiconductor (TI) |
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LM3705YABPX-643 Datasheet(HTML) 2 Page - National Semiconductor (TI) |
2 / 17 page Connection Diagram MSOP-10 Top View (looking from the coating side) micro SMD 9 Bump Package BPA09 10136902 10136901 Pin Description Pin No. Name Function micro SMD MSOP A1 2 MR Manual-Reset input. When MR is less than V MRT (Manual Reset Threshold) RESET/RESET is engaged. B1 1 V CC Power Supply input. C1 10 RESET Reset Logic Output. Pulses low for t RP (Reset Timeout Period) when triggered, and stays low whenever V CC is below the reset threshold or when MR is below VMRT. It remains low for t RP after either VCC rises above the reset threshold, or after MR input rises above V MRT (LM3704 only). RESET Reset Logic Output. RESET is the inverse of RESET (LM3705 only). C2 8 PFO Power-Fail Logic Output. When PFI is below V PFT, PFO goes low; otherwise, PFO remains high. C3 7 LLO Low-Line Logic Output. Early Power-Fail warning output. Low when V CC falls below VLLOT (Low-Line Output Threshold). This output can be used to generate an NMI (Non-Maskable Interrupt) to provide an early warning of imminent power-failure. B3 5 GND Ground reference for all signals. A3 4, 6 NC No Connect. A2 3 PFI Power-Fail Comparator Input. When PFI is less than V PFT (Power-Fail Reset Threshold), the PFO goes low; otherwise, PFO remains high. B2 9 NC No Connect. Test input used at factory only. Leave floating. www.national.com 2 |
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