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NM27C256NE200 Datasheet(PDF) 4 Page - National Semiconductor (TI) |
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NM27C256NE200 Datasheet(HTML) 4 Page - National Semiconductor (TI) |
4 / 12 page Capacitance TA ea25 C f e 1 MHz (Note 2) Symbol Parameter Conditions Typ Max Units CIN Input Capacitance VIN e 0V 6 12 pF COUT Output Capacitance VOUT e 0V 9 12 pF AC Test Conditions Output Load 1 TTL Gate and CL e 100 pF (Note 8) Input Rise and Fall Times s 5ns Input Pulse Levels 045 to 24V Timing Measurement Reference Level (Note 10) Inputs 08V and 20V Outputs 08V and 20V AC Waveforms (Notes 6 7 and 9) TLD10833 – 4 Note 1 Stresses above those listed under ‘‘Absolute Maximum Ratings’’ may cause permanent damage to the device This is stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Note 2 This parameter is only sampled and is not 100% tested Note 3 OE may be delayed up to tACC b tOE after the falling edge of CE without impacting tACC Note 4 The tDF and tCF compare level is determined as follows High to TRI-STATE the measured VOH1 (DC) b 010V Low to TRI-STATE the measured VOL1 (DC) a 010V Note 5 TRI-STATE may be attained using OE or CE Note 6 The power switching characteristics of EPROMs require careful device decoupling It is recommended that at least a 01 mF ceramic capacitor be used on every device between VCC and GND Note 7 The outputs must be restricted to VCC a 10V to avoid latch-up and device damage Note 8 TTL Gate IOL e 16 mA IOH eb400 mA CL e 100 pF includes fixture capacitance Note 9 VPP may be connected to VCC except during programming Note 10 Inputs and outputs can undershoot to b20V for 20 ns Max Note 11 CMOS inputs VIL e GND g03V VIH e VCC g03V 4 |
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