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P83C366 Datasheet(PDF) 10 Page - NXP Semiconductors |
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P83C366 Datasheet(HTML) 10 Page - NXP Semiconductors |
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10 / 92 page  1999 Mar 10 10 Philips Semiconductors Product specification Microcontrollers for PAL/SECAM TV with OSD and VST P8xCx66 family 6 MEMORY ORGANIZATION The P8xCx66 family provides 24, 32, 48 or 64 kbytes of program memory (ROM/EPROM) plus 512, 1024 or 2048 bytes of data memory (RAM) on-chip (see Table 1). The device has separate address spaces for program and data memory (see Fig.4). These devices have no external memory access capability as the RD (read), WR (write), EA (External Access), PSEN (read strobe) and ALE (Address Latch Enable) signals are not bonded out. 6.1 Data memory The P8xCx66 family contains 512, 1024 or 2048 bytes of internal RAM and 56 Special Function Registers (SFRs). Figure 4 shows the internal data memory space divided into the lower 128, the upper 128, AUX-RAM and the SFR space. The lower 128 bytes of internal RAM are organized as shown in Fig.5. The lowest 32 bytes are grouped into 4 banks of 8 registers. Program instructions refer to these registers as R0 to R7. Two bits in the Program Status Word (PSW) select which register bank is in use. The next 16 bytes above the register bank form a block of bit-addressable memory space. The 128 bits in this area can be directly addressed by the single-bit manipulation instructions. The remaining registers (30H to 7FH) are directly and indirectly byte addressable. The registers that reside at addresses above 7FH and up to FFH can only be accessed indirectly. These register addresses overlap the SFR addresses as described in Section 6.2. 6.2 Special Function Registers The upper 128 bytes are the address locations of the SFRs when accessed directly. SFRs include the port latches, timers, 7-bit PWMs, 14-bit VST PWM, ADCs and OSD control registers. These registers can only be accessed by direct addressing. There are 128 bit-addressable locations in the SFR address space (SFRs with addresses divisible by eight). Their addresses are a multiple of 08H, from 80H to F8H. (i.e., 80H, 88H, 90H, 98H etc.). See Chapter 19 for SFR list. 6.3 AUX RAM The 1792 byte (P87C766) or 768 byte (P83C766) AUX RAM, while physically located on-chip, logically occupies the first 1792/768 bytes of external data memory. As such, it is indirectly addressed in the same way as external data memory using MOVX instructions in combination with any of the registers R0, R1 or DPTR. 6.4 Addressing The P80C51 CPU has five methods for addressing source operands • Register • Direct • Register-indirect • Immediate • Base-register-plus index-register-indirect. The first three methods can be used for addressing destination operands. Most instructions have a ‘destination/source’ field that specifies the data type, addressing methods and operands involved. For operations other than MOVs, the destination operand is also a source operand. Access to memory addressing is as follows: • Registers in one of the four register banks through register direct or indirect • Internal RAM (128 bytes) through direct or register-indirect • Special Function Registers through direct • External data memory through register-indirect (for AUX RAM) • Program memory look-up tables through base-register-plus index-register-indirect. |
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