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P87C770AAR Datasheet(PDF) 11 Page - NXP Semiconductors |
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P87C770AAR Datasheet(HTML) 11 Page - NXP Semiconductors |
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11 / 80 page  1999 Jun 11 11 Philips Semiconductors Product specification Microcontrollers for NTSC TVs with On-Screen Display (OSD) and Closed Caption (CC) P8xCx70 family 8 WATCHDOG TIMER (T3) In addition to the standard timers, an 8-bit Watchdog Timer is also incorporated. When a timer overflow occurs, the microcontroller is reset. To prevent a system reset the timer must be reloaded in time by the application software. If the processor suffers a hardware/software malfunction, the software will fail to reload the timer. This failure will result in a reset upon overflow thus preventing the processor running out of control. The timer is incremented every 2 ms. The timer interval between the timer reloading and the occurrence of a reset depends on the reloaded value. This may range from 2 to 512 ms according to the following formula: T timer 256 T3 value – () 2ms × = The Watchdog Timer can only be reloaded if the condition flag WLE in SFR PCON has been previously set HIGH by software. At the moment the counter is loaded WLE is automatically cleared. The Watchdog Timer is controlled by the EW bit in SFR BWC (see Section 11.5). If EW = 1, the Watchdog Timer is enabled and the Power-down mode disabled. If EW = 0, the Watchdog Timer is disabled and the Power-down mode enabled. In the Idle mode the Watchdog Timer and reset circuitry remain active. 8.1 Watchdog Timer Register (WDT) Table 4 Watchdog Timer Register (SFR address FFH) Table 5 Description of the T3 bits 76543210 D7 D6 D5 D4 D3 D2 D1 D0 BIT SYMBOL DESCRIPTION 7 to 0 D7 to D0 Watchdog Timer reload value. These 8 bits determine the timer interval. If WDT holds FFH the timer interval is 2 ms. If WDT holds 00H the timer interval is 512 ms. handbook, full pagewidth MGL298 INTERNAL BUS 1/12 fosc PRESCALER 11-BIT WDT REGISTER (8-BIT) LOAD CLEAR LOADEN write T3 LOADEN PCON.4 PCON.0 CLEAR WLE IDL internal reset INTERNAL BUS RESET RRESET Fig.4 Watchdog Timer block diagram. |
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