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LMK04610 Datasheet(PDF) 6 Page - Texas Instruments

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Part # LMK04610
Description  Ultra-Low Noise and Low Power JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

LMK04610 Datasheet(HTML) 6 Page - Texas Instruments

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6
LMK04610
SNAS699 – JANUARY 2017
www.ti.com
Product Folder Links: LMK04610
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Copyright © 2017, Texas Instruments Incorporated
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
TJ
Junction temperature
125
°C
TA
Ambient temperature
–40
25
85
°C
TPCB
PCB temperature (measured at thermal pad)
105
°C
VDD_IO
Supply voltage for input
1.7
1.8
3.465
V
VDD_CORE
Supply voltage for digital
3.135
3.3
3.465
V
VDD_PLL1
Supply voltage for PLL1
3.135
3.3
3.465
V
VDD_PLL2CORE
Supply voltage for PLL2 Core
3.135
3.3
3.465
V
VDD_PLL2OSC
Supply voltage for PLL2 OSC
3.135
3.3
3.465
V
VDD_OSC
Supply voltage for OSCout
1.7
1.8
3.465
V
VDDO_x
Supply voltage for CLKoutX
1.7
1.8
3.465
V
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.
(2)
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3)
The junction-to-case(top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard
test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4)
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5)
The junction-to-top characterization parameter, ΨJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6)
The junction-to-board characterization parameter, ΨJB estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7)
The junction-to-case(bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
7.4 Thermal Information
THERMAL METRIC(1)
LMK04610
UNIT
RTQ (VQFN)
56 PINS
RθJA
Junction-to-ambient thermal resistance(2)
26.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance(3)
12.3
°C/W
RθJB
Junction-to-board thermal resistance(4)
4.6
°C/W
ψJT
Junction-to-top characterization parameter(5)
0.2
°C/W
ψJB
Junction-to-board characterization parameter(6)
4.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance(7)
0.8
°C/W


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