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PIC16(L)F18324 Datasheet(PDF) 7 Page - Microchip Technology |
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PIC16(L)F18324 Datasheet(HTML) 7 Page - Microchip Technology |
7 / 44 page 2014-2016 Microchip Technology Inc. DS40001738D-page 7 PIC16(L)F183XX 3.1.2 LOW-VOLTAGE PROGRAMMING (LVP) MODE The Low-Voltage Programming mode allows the devices to be programmed using VDD only, without high voltage. When the LVP bit of the Configuration Word 3 register is set to ‘1’, the low-voltage ICSP programming entry is enabled. To disable the Low-Voltage ICSP mode, the LVP bit must be programmed to ‘0’. This can only be done while in the High-Voltage Entry mode. Entry into the Low-Voltage ICSP Program/Verify mode requires the following steps: 1. MCLR is brought to VIL; 2. A 32-bit key sequence is presented on ICSPDAT, while clocking ICSPCLK. 32 clocks are required to match the sequence pattern, and a 33rd clock is required before the pattern detect goes active. The key sequence is a specific 32-bit pattern, '0100 1101 0100 0011 0100 1000 0101 0000' (more easily remembered as MCHP in ASCII). The device will enter Program/Verify mode only if the sequence is valid. The Least Significant bit of the Least Significant nibble must be shifted in first. Once the key sequence is complete, MCLR must be held at VIL for as long as Program/Verify mode is to be maintained. For low-voltage programming timing, see Figure 3-24 and Figure 3-25. Exiting Program/Verify mode is done by no longer driving MCLR to VIL (see Figure 3-24 and Figure 3-25). 3.1.3 PROGRAM/VERIFY COMMANDS These devices implement ten programming commands, each six bits in length. The commands are summarized in Table 3-1. The commands are used to erase and program the device. The commands load and use the Program Counter (PC). Commands that have data associated with them are specified to have a minimum delay of TDLY between the command and the data. After this delay, 16 clocks are required to either clock in or clock out the 14-bit data word. The first clock is for the Start bit and the last clock is for the Stop bit. Note: To enter LVP mode, the LSb of the Least Significant nibble must be shifted in first. This differs from entering the key sequence on other parts. TABLE 3-1: COMMAND MAPPING Command Mapping Data/Note Binary (MSb … LSb) Hex Load Configuration x 0 0 000 00h 0 , data (14), 0 Load Data for NVM J(1) 00 010 02h/22h 0, data (14), 0 Read Data from NVM J(1) 00 100 04h/24h 0, data (14), 0 Increment Address x 0 0 110 06h PC = PC + 1 Load PC Address x 1 1 101 1Dh 0 , data (22), 0 Begin Internally Timed Programming x 0 1 000 08h — Begin Externally Timed Programming x 1 1 000 18h — End Programming x 0 1 010 0Ah — Bulk Erase Memory x 0 1 001 09h Internally Timed Row Erase Memory x 0 0 101 05h Internally Timed Note 1: When J = 1, the Program Counter is automatically incremented by 1 (PC +1) and does not require an ‘Increment Address’ command to move the PC to the next address. When J = 0, the Program Counter is not incremented, therefore either a ‘Load PC address’ or ‘Increment Address’ command is required to move the PC to the next address. |
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