PowerPC 603e RISC Microprocessor Technical Summary

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Part 2 PowerPC 603e Microprocessor:

Implementation

The PowerPC architecture is derived from the IBM POWER architecture (Performance Optimized with

Enhanced RISC architecture). The PowerPC architecture shares the benefits of the POWER architecture

optimized for single-chip implementations. The PowerPC architecture design facilitates parallel instruction

execution and is scalable to take advantage of future technological gains.

This section describes the PowerPC architecture in general, and specific details about the implementation

of the 603e as a low-power, 32-bit member of the PowerPC processor family.

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Features—Section 2.1, “Features,” describes general features that the 603e shares with the

PowerPC microprocessor family.

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Registers and programming model—Section 2.2, “PowerPC Registers and Programming Model,”

describes the registers for the operating environment architecture common among PowerPC

processors and describes the programming model. It also describes the additional registers that are

unique to the 603e.

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Instruction set and addressing modes—Section 2.3, “Instruction Set and Addressing Modes,”

describes the PowerPC instruction set and addressing modes for the PowerPC operating

environment architecture, and defines and describes the PowerPC instructions implemented in the

603e.

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Cache implementation—Section 2.4, “Cache Implementation,” describes the cache model that is

defined generally for PowerPC processors by the virtual environment architecture. It also provides

specific details about the 603e cache implementation.

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Exception model—Section 2.5, “Exception Model,” describes the exception model of the PowerPC

operating environment architecture and the differences in the 603e exception model.

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Memory management—Section 2.6, “Memory Management,” describes generally the conventions

for memory management among the PowerPC processors. This section also describes the 603e’s

implementation of the 32-bit PowerPC memory management specification.

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Instruction timing—Section 2.7, “Instruction Timing,” provides a general description of the

instruction timing provided by the superscalar, parallel execution supported by the PowerPC

architecture and the 603e.

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System interface—Section 2.8, “System Interface,” describes the signals implemented on the 603e.

2.1 Features

The 603e is a high-performance, superscalar PowerPC microprocessor. The PowerPC architecture allows

optimizing compilers to schedule instructions to maximize performance through efficient use of the

PowerPC instruction set and register model. The multiple, independent execution units allow compilers to

optimize instruction throughput. Compilers that take advantage of the flexibility of the PowerPC

architecture can additionally optimize system performance of the PowerPC processors.

The following sections summarize the features of the 603e, including both those that are defined by the

architecture and those that are unique to the 603e implementation.

The PowerPC architecture consists of the following layers, and adherence to the PowerPC architecture can

be measured in terms of which of the following levels of the architecture is implemented:

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PowerPC user instruction set architecture (UISA)—Defines the base user-level instruction set, user-

level registers, data types, floating-point exception model, memory models for a uniprocessor

environment, and programming model for a uniprocessor environment.