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ICS9FG108YG-LFT Datasheet(PDF) 8 Page - Integrated Circuit Systems |
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ICS9FG108YG-LFT Datasheet(HTML) 8 Page - Integrated Circuit Systems |
8 / 13 page 8 Integrated Circuit Systems, Inc. ICS9FG108 Advance Information 0823—04/02/04 I 2C Table: Device Control Register, READ/WRITE ADDRESS (DC/DD) Pin # Name Control Function Type 0 1 PWD Bit 7 RW Pin 27 Bit 6 RW Pin 5 Bit 5 RW Pin 44 Bit 4 RW Pin 7 Bit 3 RW Off On Pin 26 Bit 2 RW Hardware Select Software Select 0 Bit 1 RW Driven Hi-Z 0 Bit 0 RW Down Center 0 Notes: 1. These bits reflect the state of the corresponding pins at power up, but may be written to if Byte 0, bit 2 is set to '1'. FS3 is the SEL14M_25M# pin. I 2C Table: Output Enable Register Pin # Name Control Function Type 0 1 PWD Bit 7 DIF_7 Output Control RW Disable Enable 1 Bit 6 DIF_6 Output Control RW Disable Enable 1 Bit 5 DIF_5 Output Control RW Disable Enable 1 Bit 4 DIF_4 Output Control RW Disable Enable 1 Bit 3 DIF_3 Output Control RW Disable Enable 1 Bit 2 DIF_2 Output Control RW Disable Enable 1 Bit 1 DIF_1 Output Control RW Disable Enable 1 Bit 0 DIF_0 Output Control RW Disable Enable 1 44 7 Byte 0 27 5 26 Spread Enable 1 - Enable Software Control of Frequency, Spread Enable (Spread Type always Software Control) - DIF_STOP# drive mode - SPREAD TYPE Byte 1 - - - - - - - - See Frequency Selection Table, Page 1 FS3 1 FS2 1 FS1 1 FS0 1 |
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