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ADA4084-4ACPZ-RL Datasheet(PDF) 7 Page - Analog Devices |
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ADA4084-4ACPZ-RL Datasheet(HTML) 7 Page - Analog Devices |
7 / 35 page Data Sheet ADA4084-1/ADA4084-2/ADA4084-4 Rev. H | Page 7 of 35 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating Supply Voltage ±18 V Input Voltage V− ≤ VIN ≤ V+ Differential Input Voltage1 ±0.6 V Output Short-Circuit Duration to GND Indefinite Storage Temperature Range −65°C to +150°C Operating Temperature Range −40°C to +125°C Junction Temperature Range −65°C to +150°C Lead Temperature (Soldering 60 sec) 300°C ESD Human Body Model2 4.5 kV Machine Model3 200 V Field-Induced Charged-Device Model (FICDM)4 1.25 kV 1 For input differential voltages greater than 0.6 V, limit the input current to less than 5 mA to prevent degradation or destruction of the input devices. 2 Applicable standard: MIL-STD-883, Method 3015.7. 3 Applicable standard: JESD22-A115-A (ESD machine model standard of JEDEC). 4 Applicable standard: JESD22-C101-C (ESD FICDM standard of JEDEC). Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL RESISTANCE θJA is specified for the device soldered on a 4-layer JEDEC standard printed circuit board (PCB) with zero airflow. Table 6. Thermal Resistance Package Type θJA θJC Unit 5-Lead SOT-23 (RJ-5) 219.4 155.6 °C/W 8-Lead SOIC_N (R-8) 121 43 °C/W 8-Lead MSOP (RM-8) 142 45 °C/W 8-Lead LFCSP (CP-8-12)1, 3 84 40 °C/W 14-Lead TSSOP (RU-14) 112 43 °C/W 16-Lead LFCSP (CP-16-26)2, 3 55 30 °C/W 1 Values are based on 4-layer (2S2P) JEDEC standard PCB, with four thermal vias. Exposed pad soldered to PCB. 2 Values are based on 4-layer (2S2P) JEDEC standard PCB, with nine thermal vias. Exposed pad soldered to PCB. 3 θJC measured on top of package. ESD CAUTION D2 D101 D100 D5 D4 D1 Q1 Q4 Q3 Q24 Q21 D20 Q13 Q18 Q19 Q23 Q2 FOLDED CASCADE VEE VOUT VCC VBIAS MIRROR R4 R5 R6 R7 C2 C1 R1 R2 R3 Figure 2. Simplified Schematic |
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