IQS128_16 datasheet(10/23 Pages) ETC2

Part #	IQS128

Description	DYCAL??: Intelligent Hysteresis

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IQ Switch

® ProxSense® Series

IQS128 Datasheet v3.1

Page 10 of 23

Check for latest datasheet

March 2016

6.2

LOGIC

The logic used by the device can be selected

as active HIGH or active LOW. The output

pins OUT and CTRL will function based on

this selection.

Configuration: Bank0 bit1: Logic Output

Selection

Bit

Selection

0

Software Open Drain Active Low

1

Active High

A software open drain output is implemented

for the OUT pin when configured in active

low mode. The voltage on the pull-up resistor

is limited to the IQS128 supply voltage. A

4k7-

10kΩ resistor between OUT and VDDHI

is recommended.

6.3 RF Noise on IQS128

The

IQS128

has

RF

Noise

6.3.1

Detection (ND)

The IQS128 has RF Noise Detect (ND)

functionality. If ND function is enabled, the

IQS128 is able to detect RF Noise on the

CTRL / ND pin. Further details on the

working

of

this

can

be

found

in

the

Application Notes: AZD015 and AZD015b.

IQS128 RF Noise Immunity

6.3.2

The IQS128 has advanced immunity to RF

noise

sources

such

as

GSM

cellular

telephones,

DECT,

Bluetooth

and

WIFI

devices. Design guidelines should however

be

followed

to

ensure

the

best

noise

immunity. The design of capacitive sensing

applications can encompass a large range of

situations but as a summary the following

should be noted to improve a design:

A ground plane should be placed

under the IC, except under the Cx

line.

All the tracks on the PCB must be

kept as short as possible.

The capacitor between VDDHI and

VSS as well as between VREG and

VSS, must be placed as close as

possible to the IC.

A 100 pF capacitor should be placed

in parallel with the 1uF capacitor

between VDDHI and VSS. Another

100 pF capacitor can be placed in

parallel

with

the

1uF

capacitor

between VREF and VSS.

If the device is too sensitive for a

specific

application

a

parasitic

capacitor (max 5pF) can be added

between the Cx line and ground.

Proper sense electrode and button

design principles must be followed.

Unintentional

coupling

of

sense

electrode to ground and other circuitry

must be limited by increasing the

distance to these sources.

In some instances a ground plane

some distance from the device and

sense

electrode

may

provide

significant shielding from undesired

interference.

When the capacitance between the sense

electrode and ground becomes too large the

sensitivity of the device may be influenced.

6.4

PTHR[1:0] Proximity Threshold

The

IQS128

has

4

proximity

threshold

settings indicated in CS. The proximity

threshold is selected by the designer to

obtain the desired sensitivity and noise

immunity.

A proximity event is triggered if

the CS diverges more than the selected

count from the LTA for 6 consecutive cycles.

IQS128

Configuration: Bank0 bit 4-3

PTH1:PTH0:Proximity Thresholds

Bit

Selection

00

4

(Most sensitive)

01

8

10

12

11

16

(Least sensitive)

6.5

TTHR[2:0]Touch Threshold

The IQS128 has 8 touch threshold settings

indicated in CS. The touch threshold is

selected by the designer to obtain the

desired touch sensitivity. A touch event is

triggered if the CS diverges more than the

selected

count

from

the

LTA

for

2

consecutive cycles.

In the NO-TOUCH state the CS must diverge

more than the touch threshold value below

the LTA. Operating in the TOUCH STATE,

the CS must diverge more than REL_TTHR of

the touch threshold value above the LTA.

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