SRAM

SRAM

SRAM

SRAM

SRAM

MT5C1008

Austin Semiconductor, Inc.

MT5C1008

Rev. 6.5 7/02

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

2

FUNCTIONAL BLOCK DIAGRAM

1,048,576-BIT

MEMORY ARRAY

GND

DQ8

DQ1

CE1\

CE2

OE\

WE\

A

A

A

A

A

A

A

A

A

COLUMN DECODER

A A A A A A A A

POWER

DOWN

(LSB)

(LSB)

NOTE: The two least significant row address bits (A8 and A6) are encoded using gray code.

MODE

OE\

CE1\

CE2

WE\

DQ

POWER

STANDBY

X

H

X

X

HIGH-Z

STANDBY

STANDBY

X

X

L

X

HIGH-Z

STANDBY

READ

L

L

H

H

Q

ACTIVE

READ

H

L

H

H

HIGH-Z

ACTIVE

WRITE

X

L

H

L

D

ACTIVE

TRUTH TABLE