MT5C1008ECA-45 datasheet(5/17 Pages) AUSTIN

Part #	MT5C1008ECA-45

Description	128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS

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Manufacturer	AUSTIN [Austin Semiconductor]

Direct Link	http://www.austinsemiconductor.com

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5 / 17 page

SRAM

MT5C1008

Austin Semiconductor, Inc.

MT5C1008

Rev. 6.5 7/02

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

5

AC TEST CONDITIONS

Input pulse levels ................................... Vss to 3.0V

Input rise and fall times ....................................... 5ns

Input timing reference levels ............................. 1.5V

Output reference levels ..................................... 1.5V

Output load .............................. See Figures 1 and 2

NOTES

1.

All voltages referenced to V

SS (GND).

2.

-2V for pulse width < 20ns

3.

I

CC is dependent on output loading and cycle rates.

The specified value applies with the outputs

unloaded, and f =

1

Hz.

tRC (MIN)

4.

This parameter is guaranteed but not tested.

5.

Test conditions as specified with the output loading

as shown in Fig. 1 unless otherwise noted.

6.

tLZCE, tLZWE, tLZOE, tHZCE, tHZOE and tHZWE

are specified with CL = 5pF as in Fig. 2. Transition is

measured ±200mV typical from steady state voltage,

allowing for actual tester RC time constant.

7.

At any given temperature and voltage condition,

tHZCE is less than tLZCE, and tHZWE is less than

tLZWE and tHZOE is less than tLZOE.

8.

WE\ is HIGH for READ cycle.

9.

Device is continuously selected. Chip enables and

output enables are held in their active state.

10. Address valid prior to, or coincident with, latest

occurring chip enable.

11. tRC = Read Cycle Time.

12. CE2 timing is the same as CE1\ timing. The

waveform is inverted.

13. Chip enable (CE1\, CE2) and write enable (WE\) can

initiate and terminate a WRITE cycle.

Fig. 1 Output Load

Equivalent

Fig. 2 Output Load

Equivalent

DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)

+5V

Q

255

30

480

5 pF

+5V

Q

255

480

123

1234

DON’T CARE

UNDEFINED

LOW Vcc DATA RETENTION WAVEFORM

123456789

123

1234

12345678

123

1234

123456789

123

1234

12345678

123

1234

DATA RETENTION MODE

V

DR > 2V

4.5V

V

DR

tCDR

tR

<V

SS + 0.2V

V

IH

V

IL

V

IH

V

IL

V

CC

CE1\

CE2

DESCRIPTION

SYMBOL

MIN

MAX

UNITS

NOTES

VCC for Retention Data

VDR

2

---

V

Data Retention Current

CE\ > (VCC - 0.2V)

VIN > (VCC - 0.2V)

or < 0.2V, f=0

VCC = 2V

ICCDR

1.0

mA

Chip Deselect to Data

Retention Time

tCDR

0

---

ns

4

Operation Recovery Time

tR

tRC

ns

4, 11

CONDITIONS

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