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MB95F616KPMC-G-SNE2 Datasheet(PDF) 1 Page - Cypress Semiconductor

Part # MB95F616KPMC-G-SNE2
Description  F2MC-8FX CPU core
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

MB95F616KPMC-G-SNE2 Datasheet(HTML) 1 Page - Cypress Semiconductor

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PRELIMINARY
MB95F613H/F613K/F614H
MB95F614K/F616H/F616K
New 8FX MB95610H Series
8-bit Microcontrollers
Cypress Semiconductor Corporation
198 Champion Court
San Jose
, CA 95134-1709
408-943-2600
Document Number: 002-04698 Rev. *A
Revised April 8, 2016
The MB95610H Series is a series of general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the
microcontrollers of these series contain a variety of peripheral resources.
Features
F2MC-8FX CPU core
Instruction set optimized for controllers
Multiplication and division instructions
16-bit arithmetic operations
Bit test branch instructions
Bit manipulation instructions, etc.
Clock
Selectable main clock source
Main oscillation clock (up to 16.25 MHz, maximum machine
clock frequency: 8.125 MHz)
External clock (up to 32.5 MHz, maximum machine clock
frequency: 16.25 MHz)
Main CR clock (4 MHz 2%)
Main PLL clock / Main CR PLL clock (Main oscillation clock
= 4 MHz, Main CR clock = 4 MHz)
• Both main oscillation clock and main CR clock can be mul-
tiplied by a PLL multiplication rate.
• The frequency of the main PLL clock / main CR PLL clock
becomes 8 MHz when the PLL multiplication rate is 2.
• he frequency of the main PLL clock / main CR PLL clock
becomes 10 MHz when the PLL multiplication rate is 2.5.
• he frequency of the main PLL clock / main CR PLL clock
becomes 12 MHz when the PLL multiplication rate is 3.
• he frequency of the main PLL clock / main CR PLL clock
becomes 16 MHz when the PLL multiplication rate is 4.
Selectable subclock source
Suboscillation clock (32.768 kHz)
External clock (32.768 kHz)
Sub-CR clock (Typ: 100 kHz, Min: 50 kHz, Max: 150 kHz)
Timer
8/16-bit composite timer  2 channels
8/16-bit PPG  2 channels
16-bit reload timer  1 channel
Event counter  1 channel
Time-base timer  1 channel
Watch counter  1 channel
Watch prescaler  1 channel
UART/SIO
 2 channels
Full duplex double buffer
Capable of clock asynchronous (UART) serial data transfer and
clock synchronous (SIO) serial data transfer
I2C bus interface
 1 channel
Built-in wake-up function
External interrupt
 8 channels
Interrupt by edge detection (rising edge, falling edge, and both
edges can be selected)
Can be used to wake up the device from different low power
consumption (standby) modes
8/10-bit A/D converter
 4 channels
8-bit or 10-bit resolution can be selected.
LCD controller (LCDC)
LCD output can be selected from 52 SEG  4 COM or 48 SEG
 8 COM.
Internal divider resistor whose resistance value can be selected
from 10 k
 or 100 k through software
Interrupt in sync with the LCD module frame frequency
Blinking function
Inverted display function
Low power consumption (standby) modes
There are four standby modes as follows:
Stop mode
Sleep mode
Watch mode
Time-base timer mode
In standby mode, two further options can be selected: normal
standby mode and deep standby mode.
I/O port
MB95F613H/F614H/F616H (no. of I/O ports: 40)
General-purpose I/O ports (CMOS I/O): 39
General-purpose I/O ports (N-ch open drain): 1
MB95F613K/F614K/F616K (no. of I/O ports: 41)
General-purpose I/O ports (CMOS I/O): 39
General-purpose I/O ports (N-ch open drain): 2
On-chip debug
1-wire serial control
Serial writing supported (asynchronous mode)


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