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MB91F575CPMC Datasheet(PDF) 1 Page - Cypress Semiconductor |
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MB91F575CPMC Datasheet(HTML) 1 Page - Cypress Semiconductor |
1 / 163 page MB91570 Series 32-bit Microcontroller Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 002-04725 Rev.*A Revised March 16, 2016 This series is Cypress 32-bit microcontroller designed for automotive and industrial control applications. It contains the FR81S CPU that is compatible with the FR family. The FR81S has a high level performance among the Cypress FR family by enhancing CPU instruction pipeline and load store processing, and improving internal bus transfer. It is best suited for application control for automotive. Features FR81S CPU Core 32-bit RISC, load/store architecture, 5-stage pipeline Maximum operating frequency: 80 MHz (Source oscillation = 4.0 MHz and 20 multiplied ( PLL clock multiplication system )) General-purpose register : 32-bit ×16 sets 16-bit fixed length instructions ( basic instruction ), 1 instruction per cycle Instructions appropriate to embedded applications Memory-to-memory transfer instruction Bit processing instruction Barrel shift instruction etc. High-level language support instructions Function entry/exit instructions Register content multi-load and store instructions Bit search instructions Logical 1 detection, 0 detection, and change-point detection Branch instructions with delay slot Decrease overhead during branch process Register interlock function Easy assembler writing Built-in multiplier and instruction level support Signed 32-bit multiplication : 5 cycles Signed 16-bit multiplication : 3 cycles Interrupt ( PC/PS saving ) 6 cycles ( 16 priority levels ) The Harvard architecture allows simultaneous execution of program and data access. Instruction compatibility with the FR family Built-in memory protection function ( MPU ) Eight protection areas can be specified commonly for instructions and the data. Control access privilege in both privilege mode and user mode. Built-in FPU (floating point arithmetic) IEEE754 compliant Floating-point register 32-bit × 16 sets Peripheral Functions Clock generation (equipped with SSCG function) Main oscillation (4MHz) Sub oscillation (32kHz ) or no sub oscillation PLL multiplication rate : 1 to 20 times Built-in Program flash memory capacity MB91F575 : 512 + 64KB MB91F577 : 1024 + 64KB MB91F578 : 1536 + 64KB MB91F579 : 2048 + 64KB Built-in Data flash memory (WorkFlash) capacity 64KB Built-in RAM capacity Main RAM MB91F575 : 40KB MB91F577 : 64KB MB91F578 : 96KB MB91F579 : 128KB Backup RAM MB91F575/7 : 8KB MB91F578/9 : 16KB General-purpose ports [LQFP-144] 111 (none sub oscillation ), 109 (with sub oscillation ) Included I 2C pseudo open drain ports : 4 P057 : Input only [LQFP-208] 159 (none sub oscillation ), 157 (with sub oscillation ) Included I 2C pseudo open drain ports : 4 P057 : Input only External bus interface 22-bit address, 16-bit data 23 pins of 9-bit address, 8-bit data, ASX, CS0X, CS1X, RDX, WR0X, and WR1X can select 5V/3.3V by the VCCE power supply DMA Controller Up to 16 channels can be started simultaneously. 2 transfer factors ( Internal peripheral request and software ) |
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