Document Number: 002-14837 Rev. *L

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CYW20732A0

1.4 ADC Port

The CYW20732 contains a 16-bit ADC (effective number of bits is 10).

Additionally:

The ADC consists of an analog ADC core that performs the actual analog-to-digital conversion and digital hardware that processes

the output of the ADC core into valid ADC output samples. Directed by the firmware, the digital hardware also controls the input

The ADC input range is selectable by firmware control:

ADC modes are defined in Table 2.

1.5 Serial Peripheral Interface

The CYW20732 has two independent SPI interfaces. One is a master-only interface and the other can be either a master or a slave.

Each interface has a 16-byte transmit buffer and a 16-byte receive buffer. To support more flexibility for user applications, the

CYW20732 has optional I/O ports that can be configured individually and separately for each functional pin as shown in Table 3,

Table 4, and Table 5. The CYW20732 acts as a SPI master device that supports 1.8V or 3.3V SPI slaves. The CYW20732 can also

act as an SPI slave device that supports a 1.8V or 3.3V SPI master.

Table 2. ADC Modes

Mode

ENOB (Typical)

Maximum Sampling Rate (kHz)

a.Settling time after switching channels.

0

13

5.859

171

1

12.6

11.7

85

212

46.875

21

3

11.5

93.75

11

410

187

5